Xilinx Virtex-5 LXT, Руководство пользователя

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Virtex-5 LXT/SXT/FXT FPGA Prototype Platform www.xilinx.com 11
UG229 (v3.0.1) May 21, 2008
Overview
R
Block Diagram
Figure 1 shows a block diagram of the board.
X-Ref Target - Figure 1
Figure 1: Virtex-5 LXT/SXT/FXT FPGA Prototype Platform Block Diagram
Virtex-5 DUT
Up s tre a m
S y s tem ACE
Interf a ce
Connector
U s er LED s
UG229_01_05120 8
DONE
LED INIT
LED
VBATT
PROGRAM
U s er RE S ET
To Te s t Point s
on All Pin s
Config u r a tion
Up s tre a m
Interf a ce
Connector
Down s tre a m
Interf a ce
Connector
Down s tre a m
S y s tem ACE
Interf a ce
Connector
LVTTL
2x
2x Diff P a ir
Clock s
S MA S MA
Power B us a nd S witche s
5V J a ck 5V Brick -or-
VCC J a ck
VCCO J a ck
VCCAUX J a ck
VCCINT
VCCO
VCCAUX
VCC 3 VCC1V 8
2x
2x Diff P a ir
Clock s
S MA
Pl a tform Fl as h,
S PI, BPI, JTAG
S y s tem
Monitor
S MA
GTP/GTX Tr a n s ceiver Power Su pply
AVCC
VCCO
AVCCPLL
AVTTTX
AVTTRX
The GTP/GTX tr a n s ceiver power su pply n a me s
might h a ve the prefix MGT in other Xilinx
doc u ment a tion. N a me s with a nd witho u t the
MGT prefix a re s ynonymo us to e a ch other.
NOTE:
LVTTL
2x Diff P a ir
GTP/GTX Clock s
S MA S MA