Xilinx Spartan-3A DSP FPGA Series, Техническое справочное руководство

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XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1
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Table 7 FPGA I/O bank voltage rail
FPGA bank I/O voltage rail
0 Adjustable (2.5 V or 3.3 V)
1 1.8 V
2 3.3 V
3 Adjustable (1.5 V, 1.8 V, 2.5 V, or 3.3 V)
21. Clock generator
IDT IDT5V9885PFGI. The clock generator is used to generate different clocks on the XtremeDSP Spartan-
3A DSP Development Board. The following table summarizes the default settings of output clocks. The clock
generator can be programmed through the I
2
C interface. See
I
2
C bus addressing
for details.
Table 8 Clock generator default settings
Clock output Default frequency Clock usage
1 25 MHz Ethernet PHY clock.
2 14.31818 MHz Audio codec clock.
3 12 MHz USB clock.
4_P 33 MHz System ACE clock.
4_N 33 MHz FPGA clock (FPGA pin AE13).
5_P 200 MHz FPGA differential clock P (FPGA pin AA13).
5_N 200 MHz FPGA differential clock N (FPGA pin Y13).
6 27 MHz FPGA clock (FPGA pin AF13).
22. Program and reset buttons
Button S10 is used to force the FPGA to be reprogrammed and button S9 is used to force the System ACE to
reset.
23. 64-Kb I
2
C EEPROM
The I
2
C EEPROM 24LC64 can be used to store non-volatile data such as an Ethernet MAC address. The
EEPROM is accessible through the I
2
C bus. See
I
2
C bus addressing
for details. The EEPROM write-protect
is disabled on the board. I2C bus pull-up resistors are provided on the board.
The I
2
C bus is extended to the FMC expansion connector so that the board can access additional I
2
C devices
and share the I
2
C controller in the FPGA.
Table 9 I
2
C FPGA pin assignments
I
2
C signal FPGA pin Description
IIC_SCLK AF23 I
2
C clock
IIC_SDAT AE25 I
2
C data