ML605/SP605 Hardware Tutorial
15
UG669 (v3.0) March 15, 2011
System Design Flow
Examining the System
The System Assembly View (SAV) of the design provides visibility of the MicroBlaze
Processor Subsystem bus interfaces, port connections, and address map.
Note:
Refer to UG683,
EDK Concepts, Tools, and Techniques
for additional details or instructions
for any of the steps outlined in this section of the tutorial.
Bus Interfaces
1.
To examine the bus structure of the MicroBlaze Processor Subsystem, select the
System Assembly View
tab and then select the
Bus Interfaces
tab along the top edge
of the workspace as shown in
For MicroBlaze masters (Instruction Cache (IC), Data Cache (DC), and Data Port (DP)),
both AXI_MM and AXI_Lite interconnects are used. Two Local Memory Buses (LMB)
are used by MicroBlaze to interface to the local BRAM memory for the processor. These
bus interfaces on MicroBlaze are seen by clicking the
+
to the left of the microblaze_0
).
