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ML605 Hardware User Guide

37

UG534 (v1.9) February 26, 2019

Detailed Description

The PCIe interface obtains its power from the DC power supply provided with the ML605
or through the 12V ATX power supply connector. The PCIe edge connector is not used for
any power connections.

The board can be powered by one of two 12V sources; J60, a 6-pin (2x3) molex-type
connector; and J25, a 4-pin (inline) ATX disk drive type connector.

The 6-pin molex-type connector provides 60W (12V @ 5A) from the AC power adapter
provided with the board while the 4-pin ATX disk drive connector is provided for users
who want to power their board while it is installed inside a PC chassis.

For applications requiring additional power, such as the use of expansion cards drawing
significant power, a larger AC adapter might be required. If a different AC adapter is used,
its load regulation should be better than ±10%.

ML605 power switch SW2 turns the board on and off by controlling the 12V supply to the
board.

Caution!

Never apply power to the power brick connector (J60) and the 4-pin ATX disk drive

connector (J25) at the same time as this will result in damage to the board. See

.

Never connect an auxiliary PCIe 6-pin molex power connector to J60 6-pin molex on the ML605
board as this could result in damage to the PCIe motherboard and/or ML605 board. The 6-pin
molex connector is marked with a

no PCIe power

label to warn users of the potential hazard.

AA3

PCIE_RX7_P

B45

PETp7

Integrated Endpoint block
receive pair

GTXE1_X0Y8

AA4

PCIE_RX7_N

B46

PETn7

P6

PCIE_100M_MGT0_P

U14.16

Q0

Sourced from U14 ICS854104

IBUF_

GTXE1_X0Y6

P5

PCIE_100M_MGT0_N

U14.15

NQ0

clock driver

V6

PCIE_250M_MGT1_P

U9.18

Q

Sourced from U9 ICS874001

IBUF_

GTXE1_X0Y4

V5

PCIE_250M_MGT1_N

U9.17

NQ

clock multiplier/driver

U14.6

PCIE_CLK_QO_P

A13

Integrated Endpoint block
differential clock pair from PCIe
edge connector

U14.7

PCIE_CLK_QO_N

A14

REFCLK-

J42.2,4,6

PCIE_PRSNT_B

A1

PRSNT#1

J42 Lane Size Select jumper

AD22

PCIE_WAKE_B

B11

WAKE#

Integrated Endpoint block wake
signal, not connected on ML605
board

AE13

PCIE_PERST_B

A11

PERST

Integrated Endpoint block reset
signal

Notes:

1. PCIE_TXn_P/N pairs are capacitively coupled to FPGA
2. PCIE_100M_MGT0_P/N pairs are capacitively coupled to FPGA
3. PCIE_250M_MGT1_P/N pairs are capacitively coupled to FPGA
4. PCIE_PERST_B is level-shifted by U32
5. For ML605, access is through MGT Banks 114 and 115

Table 1-8:

PCIe Edge Connector Connections

(Cont’d)

U1 FPGA

Pin

Schematic Net Name

P1 PCIe Edge Connector

Description

Package

Placement

Pin Number

Pin Name

«
...
35
36
37
38
39
...
»

Содержание ML605

Страница 1: ...ML605 Hardware User Guide UG534 v1 9 February 26 2019...

Страница 2: ...products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in such critical appli...

Страница 3: ...stability in section Oscillator Differential Added Table 1 32 and table notes in Table 1 31 Revised the FPGA U1 Pins for IIC_SDA_MAIN and IIC_SCL_MAIN in Table 1 18 06 19 12 1 7 Added Ref 4 link to O...

Страница 4: ...ML605 Hardware User Guide www xilinx com UG534 v1 9 February 26 2019...

Страница 5: ...605 Flash Boot Options 23 5 System ACE CF and CompactFlash Connector 27 6 USB JTAG 29 7 Clock Generation 30 Oscillator Differential 30 Oscillator Socket Single Ended 2 5V 30 SMA Connectors Differentia...

Страница 6: ...C Connector 60 20 VITA 57 1 FMC LPC Connector 66 21 Power Management 68 AC Adapter and Input Power Jack Switch 68 Onboard Power Regulation 69 22 System Monitor 72 Configuration Options 77 Appendix A D...

Страница 7: ...lable for download at www xilinx com support documentation virtex 6 htm Virtex 6 Family Overview The features and product selection of the Virtex 6 family are outlined in this overview Virtex 6 FPGA D...

Страница 8: ...Guide This guide describes the dedicated Tri Mode Ethernet Media Access Controller available in all Virtex 6 FPGAs except the XC6VLX760 Virtex 6 FPGA DSP48E1 Slice User Guide This guide describes the...

Страница 9: ...Additional Information Additional information and support material is located at www xilinx com ml605 This information includes Current version of this user guide in PDF format Example design files f...

Страница 10: ...r differential Socketed 2 5V oscillator single ended SMA connectors differential SMA connectors for MGT clocking 8 Multi Gigabit Transceivers GTX MGTs FMC HPC connector FMC LPC connector SMA PCIe SFP...

Страница 11: ...IO connectors 2 LCD character display 16 characters x 2 lines 18 Switches Power on off slide switch System ACE CF reset pushbutton System ACE CF bitstream image select DIP switch Configuration MODE DI...

Страница 12: ...Circuit VITA 57 1 FMC HPC Connector VITA 57 1 FMC LPC Connector Virtex 6 FPGA XC6VLX240T 1FFG1156 System ACE CF S A CompactFlash S A 8 bit MPU I F User LED SW User DIP SW User LCD 200 MHz LVDS Clock S...

Страница 13: ...your clothing The wrist strap protects components from ESD on the body only Handle the adapter by its bracket or edges only Avoid touching the printed circuit board or the connectors Put the adapter d...

Страница 14: ...200 MHz oscillator on backside SiTime 200 MHz 2 5V LVDS OSC 30 b Oscillator socket single ended MMD Components 66 MHz 2 5V 30 c SMA connectors SMA pair 30 d MGT REFCLK SMA connectors SMA pair 30 8 GTX...

Страница 15: ...3 c System ACE CF Image Select 4 pole DIP switch active High 25 d Mode Switch 6 pole DIP switch active High 25 19 FMC HPC connector Samtec ASP 134486 01 16 19 20 FMC LPC connector Samtec ASP 134603 01...

Страница 16: ...ult mode setting see Table A 34 is M 2 0 010 which selects Master BPI Up at board power on Switch S1 position 4 must be OFF to disable the System ACE controller from attempting to boot if a CF card is...

Страница 17: ...in Performance up to DDR3 1066 Table 1 3 Voltage Rails U1 FPGA Bank I O Rail Voltage Bank 0 VCC2V5_FPGA 2 5V Bank 12 1 FMC_VIO_B_M2C 2 5V Bank 13 VCC2V5_FPGA 2 5V Bank 14 VCC2V5_FPGA 2 5V Bank 15 VCC2...

Страница 18: ...adjacent banks as follows CONFIG DCI_CASCADE 36 35 CONFIG DCI_CASCADE 26 25 Table 1 4 shows the connections and pin numbers for the DDR3 SODIMM Table 1 4 DDR3 SODIMM Connections U1 FPGA Pin Schematic...

Страница 19: ...DDR3_D19 53 DQ19 G12 DDR3_D20 40 DQ20 G13 DDR3_D21 42 DQ21 F14 DDR3_D22 50 DQ22 H14 DDR3_D23 52 DQ23 C19 DDR3_D24 57 DQ24 G20 DDR3_D25 59 DQ25 E19 DDR3_D26 67 DQ26 F20 DDR3_D27 69 DQ27 A20 DDR3_D28 5...

Страница 20: ...G27 DDR3_D52 164 DQ52 A28 DDR3_D53 166 DQ53 E24 DDR3_D54 174 DQ54 G25 DDR3_D55 176 DQ55 F28 DDR3_D56 181 DQ56 B31 DDR3_D57 183 DQ57 H29 DDR3_D58 191 DQ58 H28 DDR3_D59 193 DQ59 B30 DDR3_D60 180 DQ60 A3...

Страница 21: ...3_DQS6_N 169 DQS6_N H27 DDR3_DQS6_P 171 DQS6_P D30 DDR3_DQS7_N 186 DQS7_N C30 DDR3_DQS7_P 188 DQS7_P F18 DDR3_ODT0 116 ODT0 E17 DDR3_ODT1 120 ODT1 E18 DDR3_RESET_B 30 RESET_B K18 DDR3_S0_B 114 S0_B K1...

Страница 22: ...PC To achieve the fastest configuration speed the FPGA mode pins are set to Slave SelectMAP and the onboard 47 MHz clock source external to the FPGA is used for configuration Configuration DIP switch...

Страница 23: ...upper half of U4 to be chosen as a data source Table 1 5 shows the connections and pin numbers for the boot flash devices X Ref Target Figure 1 3 Figure 1 3 Platform Flash and BPI Flash Block Diagram...

Страница 24: ...22 A8 A21 AL9 FLASH_A22 9 A23 G1 A22 AA23 FLASH_A23 26 A24 NC A23 AF24 FLASH_D0 34 DQ0 F2 DQ00 AF25 FLASH_D1 36 DQ1 E2 DQ01 W24 FLASH_D2 39 DQ2 G3 DQ02 V24 FLASH_D3 41 DQ3 E4 DQ03 H24 FLASH_D4 47 DQ4...

Страница 25: ...24 FPGA_FCS_B 2 NA 1 NA 1 NA 1 NA 1 NA 1 PLATFLASH_FCS_B 3 NA 1 NA 1 B4 E NA 1 FLASH_CE_B 4 30 OE NA 1 NA 1 Notes 1 Not Applicable 2 FPGA control flash memory select signal connected to pin U10 3 3 Pl...

Страница 26: ...esign or EDK embedded memory controller EMC peripheral to the flash through the pins defined in Table 1 5 The Platform Flash XL defaults to a synchronous read mode Typically the Platform Flash XL requ...

Страница 27: ...he DOS 8 3 short file name format This means that the folder names can be up to eight characters long and cannot contain the following reserved characters This DOS 8 3 file name restriction does not a...

Страница 28: ...E_D2 63 MPD02 AP16 SYSACE_D3 62 MPD03 AG16 SYSACE_D4 61 MPD04 AH15 SYSACE_D5 60 MPD05 AF16 SYSACE_D6 59 MPD06 AN15 SYSACE_D7 58 MPD07 AC15 SYSACE_MPA00 70 MPA00 AP15 SYSACE_MPA01 69 MPA01 AG17 SYSACE_...

Страница 29: ...nd Figure 1 6 When either or both VITA 57 1 FMC expansion connectors are populated with an expansion module that has a JTAG chain the respective jumper s must be set to connect pins 2 3 in order to in...

Страница 30: ...flash or the Platform Flash XL from the JTAG USB J22 connector For an overview on configuring the FPGA see Configuration Options 7 Clock Generation There are three FPGA fabric clock sources available...

Страница 31: ...m 31 UG534 v1 9 February 26 2019 Detailed Description X Ref Target Figure 1 7 Figure 1 7 ML605 Oscillator Socket Pin 1 Location Identifiers Silkscreened outline has beveled corner UG534_07_092109 Sock...

Страница 32: ...vided to the FPGA using differential clock signals through the onboard 50 SMA connectors J58 P J55 N This differential user clock has the signal names USER_SMA_CLOCK_N and USER_SMA_CLOCK_P X Ref Targe...

Страница 33: ..._REFCLK_C_N1 J30 32K10K 400E3 J31 32K10K 400E3 SMA_REFCLK_N SMA_REFCLK_P SMA_REFCLK_C_P1 GND1 GND2 GND3 GND4 SIG SIG GND5 GND6 GND7 GND1 GND2 GND3 GND4 GND5 GND6 GND7 2 3 4 5 6 7 8 2 3 4 5 6 7 8 C61 1...

Страница 34: ...ngers HCSL 250 MHz LVDS GTX_X0Y19 GTX_X0Y18 GTX_X0Y17 GTX_X0Y16 GTX_X0Y15 GTX_X0Y14 GTX_X0Y13 GTX_X0Y12 GTX_X0Y11 GTX_X0Y10 GTX_X0Y09 GTX_X0Y08 GTX_X0Y07 GTX_X0Y06 GTX_X0Y05 GTX_X0Y04 GTX_X0Y03 GTX_X0...

Страница 35: ...jumper J42 as shown in the figure below The default lane size selection is 1 lane J42 pins 1 and 2 jumpered X Ref Target Figure 1 11 Figure 1 11 PCIe MGT Banks 114 and 115 Clocking UG534_11_100809 P1...

Страница 36: ...block transmit pair GTXE1_X0Y11 P2 PCIE_TX4_N A36 PERn4 T1 PCIE_TX5_P A39 PERp5 Integrated Endpoint block transmit pair GTXE1_X0Y10 T2 PCIE_TX5_N A40 PERn5 V1 PCIE_TX6_P A43 PERp6 Integrated Endpoint...

Страница 37: ...PCIe 6 pin molex power connector to J60 6 pin molex on the ML605 board as this could result in damage to the PCIe motherboard and or ML605 board The 6 pin molex connector is marked with a no PCIe powe...

Страница 38: ...nnected to MGT Bank 116 on the FPGA The SFP module serial ID interface is connected to the SFP IIC bus see 15 IIC Bus for more information The control and status signals for the SFP module are connect...

Страница 39: ...r Pin Number Pin Name E3 SFP_RX_P 13 RDP_13 E4 SFP_RX_N 12 RDN_12 C3 SFP_TX_P 18 TDP_18 C4 SFP_TX_N 19 TDN_19 V23 SFP_LOS 8 LOS AP12 SFP_TX_DISABLE 1 3 TX_DISABLE Notes 1 The SFP TX Disable pin 3 is d...

Страница 40: ...Definition and Value Bit 1 Definition and Value Bit 0 Definition and Value X Ref Target Figure 1 13 Figure 1 13 Ethernet SGMII Clock 125 MHz VDDA_SGMIICLK ICS84402II VDDA VDD VDD_SGMIICLK SGMIICLK_QO...

Страница 41: ...D6 AC13 PHY_RXD7 120 RXD7 AH12 PHY_TXC_GTXCLK 14 GTXCLK AD12 PHY_TXCLK 10 TXCLK AH10 PHY_TXER 13 TXER AJ10 PHY_TXCTL_TXEN 16 TXEN AM11 PHY_TXD0 18 TXD0 AL11 PHY_TXD1 19 TXD1 AG10 PHY_TXD2 20 TXD2 AG11...

Страница 42: ...are for example HyperTerm or TeraTerm The VCP device driver must be installed on the host PC prior to establishing communications with the ML605 Refer to the evaluation kit Getting Started Guide for d...

Страница 43: ...C Data Sheet DS581 for more information Ref 20 Table 1 16 USB Controller Connections U1 FPGA Pin Schematic Net Name U81 USB Controller Pin Number Pin Name Y32 USB_A0_LS 52 GPIO19_A0_CS0_52 W26 USB_A1_...

Страница 44: ...by way of the video IIC bus The DVI connector Table 1 17 supports the IIC protocol to allow the board to read the monitor s configuration parameters These parameters can be read by the FPGA using the...

Страница 45: ...C interface 8Kb NV Memory U6 FMC HPC connector J64 DDR3 SODIMM Socket J1 The DVI IIC bus hosts two items FPGA U1 Bank 34 DVI IIC interface DVI codec U38 and DVI connector J63 The LPC IIC bus hosts two...

Страница 46: ...MICRO M24C08 WDW6TP FMC HPC COLUMN C 2 Kb EEPROM on any FMC LPC Mezzanine Card DDR3 SODIMM SOCKET P4 SFP MODULE CONNECTOR IIC_SDA_MAIN SFP_MOD_DEF2 SFP_MOD_DEF1 IIC_SDA_DVI_F BANK 13 BANK 34 BANK 33...

Страница 47: ...IC Bus Interface Data Sheet DS606 Ref 21 X Ref Target Figure 1 15 Figure 1 15 IIC Memory U6 UG534_15_072109 IIC SCL MAIN VCC3V3 VCC3V3 VCC3V3 IIC Address 0b1010100 IIC SDA MAIN U6 SCL WP C65 X5R 10V 0...

Страница 48: ...CD9240 controllers report power good DS13 FPGA_DONE GREEN DONE FPGA configured successfully DS23 LED_GRN GREEN STATUS USB JTAG Connection Status Dual LED LED_RED RED DS25 12V GREEN 12V 12V Power On DS...

Страница 49: ...board They are mounted in right angle plastic housings and can be seen on the connector end of the board This cluster of six LEDs is installed adjacent to the RJ45 Ethernet jack P2 X Ref Target Figure...

Страница 50: ...provides the following user and general purpose I O capabilities User LEDs 8 with parallel wired GPIO male pin header User Pushbutton 5 switches with associated direction LEDs CPU Reset pushbutton swi...

Страница 51: ...R16 27 4 1 1 16W R15 27 4 1 1 16W R14 27 4 1 1 16W R13 27 4 1 1 16W R11 27 4 1 1 16W R10 27 4 1 1 16W R9 27 4 1 1 16W R8 27 4 1 1 16W R7 27 4 1 1 16W R6 27 4 1 1 16W R5 27 4 1 1 16W 1 2 1 2 1 2 1 2 1...

Страница 52: ...s are assigned as GPIO and the sixth is assigned as CPU_RESET Figure 1 19 and Table 1 22 describe the pushbutton switches Table 1 21 User LED Connections FPGA U1 Pin Schematic Net Name GPIO J62 Pin Co...

Страница 53: ...arget Figure 1 20 Figure 1 20 User 8 pole DIP Switch UG534_20_072109 GPIO DIP SW1 GPIO DIP SW2 GPIO DIP SW3 GPIO DIP SW4 GPIO DIP SW5 GPIO DIP SW6 GPIO DIP SW7 GPIO DIP SW8 1 2 3 4 5 6 7 8 16 SW1 VCC1...

Страница 54: ...21 and Table 1 24 X Ref Target Figure 1 21 Figure 1 21 User SMA GPIO UG534_21_072109 USER SMA GPIO N J56 32K10K 400E3 J76 32K10K 400E3 GND1 SIG 1 1 SIG GND2 GND3 GND4 GND5 GND6 GND7 GND1 GND2 GND3 GND...

Страница 55: ...e LCD module has a connector that allows the LCD to be removed from the board to access to the components below it Caution Care should be taken not to scratch or damage the surface of the LCD window X...

Страница 56: ...d power system X Ref Target Figure 1 23 Figure 1 23 Power On Off Slide Switch SW2 UG534_23 _081209 N C 12v 12v N C COM COM 1 4 2 3 6 1 2 3 4 5 NC NC 39 30 1060 ATX Peripheral Cable Connector can plug...

Страница 57: ...is high enabled by closing DIP switch S1 switch 4 the System ACE CF controller configures the FPGA from the CompactFlash card when a card is inserted or the SYSACE RESET button is pressed See 5 System...

Страница 58: ...and CompactFlash Connector for more details about the System ACE controller Note S1 switch 4 is the System ACE controller enable switch When ON this switch allows the System ACE to boot at power on i...

Страница 59: ...ed to select the upper or lower half of flash memory U4 as the source of the FPGA bitstream image When FLASH_A23 is High the upper half of the address is selected When FLASH_A23 is Low the lower half...

Страница 60: ...connector provides connectivity for 160 single ended or 80 differential user defined signals 10 MGTs 2 MGT clocks 4 differential clocks 159 ground 15 power connections Of the above signal and clock c...

Страница 61: ...AP5 A3 FMC_HPC_DP1_M2C_N AE4 B13 FMC_HPC_DP7_M2C_N AP6 A6 FMC_HPC_DP2_M2C_P AF5 B16 FMC_HPC_DP6_M2C_P AM5 A7 FMC_HPC_DP2_M2C_N AF6 B17 FMC_HPC_DP6_M2C_N AM6 A10 FMC_HPC_DP3_M2C_P AG3 B20 FMC_HPC_GBTC...

Страница 62: ...BUF 2 U88 17 E2 FMC_HPC_HA01_CC_P AD29 F1 FMC_HPC_PG_M2C_LS 1 J27 E3 FMC_HPC_HA01_CC_N AC29 F4 FMC_HPC_HA00_CC_P AE33 E6 FMC_HPC_HA05_P AB27 F5 FMC_HPC_HA00_CC_N AF33 E7 FMC_HPC_HA05_N AC27 F7 FMC_HPC...

Страница 63: ..._HPC_LA08_N AJ22 H13 FMC_HPC_LA07_P AK21 G15 FMC_HPC_LA12_P AM21 H14 FMC_HPC_LA07_N AJ21 G16 FMC_HPC_LA12_N AL21 H16 FMC_HPC_LA11_P AM22 G18 FMC_HPC_LA16_P AP22 H17 FMC_HPC_LA11_N AN22 G19 FMC_HPC_LA1...

Страница 64: ...C_HB01_N AM32 K26 FMC_HPC_HB00_CC_N AG30 J27 FMC_HPC_HB07_P AJ34 K28 FMC_HPC_HB06_CC_P AF26 J28 FMC_HPC_HB07_N AH34 K29 FMC_HPC_HB06_CC_N AE26 J30 FMC_HPC_HB11_P AJ29 K31 FMC_HPC_HB10_P AF28 J31 FMC_H...

Страница 65: ...r HPC Connector Voltage Supply Allowable Voltage Range No Pins Max Amps Tolerance Max Capacitive Load VADJ Fixed 2 5V 4 4 5 1000 uF VIO_B_M2C 0 VADJ 2 1 15 5 500 uF VREF_A_M2C 0 VADJ 1 1 mA 2 10 uF VR...

Страница 66: ...connectivity for 68 single ended or 34 differential user defined signals 1 MGT 1 MGT clock 2 differential clocks 61 ground 10 power connections Of the above signal and clock connectivity capability t...

Страница 67: ...10_P F30 D14 FMC_LPC_LA09_P L25 C15 FMC_LPC_LA10_N G30 D15 FMC_LPC_LA09_N L26 C18 FMC_LPC_LA14_P C33 D17 FMC_LPC_LA13_P D34 C19 FMC_LPC_LA14_N B34 D18 FMC_LPC_LA13_N C34 C22 FMC_LPC_LA18_CC_P L29 D20...

Страница 68: ...PC ATX power supply 6 pin connector into ML605 connector J60 The ATX 6 pin connector has a different pinout than ML605 J60 and connecting the ATX 6 pin connector will damage the ML605 and void the bo...

Страница 69: ...r 2 UCD9240PFC U25 Switching Regulator UCD7230RG 1 00V 6A max U35 Switching Regulator UCD7230RG 1 20V 6A max U36 Switching Module PTD08A010W 1 5V 10A max U20 Switching Module PTD08A010W 3 3V 10A max U...

Страница 70: ...3 30V 44 TPS79518DCQR U79 500 mA Fixed Linear Regulator VCC_1V8 1 80V 45 TPS51200DRCT U17 3A DDR3 VTERM Tracking Linear Regulator VTTDDR 0 75V 45 TPS51200DRCT U17 10 mA Tracking Reference output VTTVR...

Страница 71: ...software package which includes several tools capable of communicating with the UCD92xx series of controllers from a Windows based host computer via the PMBus pod The ML605 onboard connector J3 is wi...

Страница 72: ...d analog power supply pins and supports the use of an external 1 25V reference IC U23 for the analog to digital conversion process An option using jumper J19 to select an on chip reference is also pro...

Страница 73: ...A 1V Vccint core supply are also available on this header By connecting header pins 9 to 11 and 10 to 12 using jumpers the system monitor can be used to monitor the FPGA core current and power consump...

Страница 74: ...o monitor the 12V supply voltage and to provide a reference voltage to an instrumentation amplifier InAmp The voltage on the auxiliary channel 12 is equal to supply voltage divided by 24 0 5V The InAm...

Страница 75: ...t at header J59 as shown in Figure 1 32 The fan PWM signal is generated by the FPGA and the tach input can be used to close the control loop and regulate the fan speed Alternatively the FPGA temperatu...

Страница 76: ...to provide information on the FPGA power supplies temperature and power consumption In addition the UART interface can be used to margin the FPGA supplies over the PMBus The System Monitor functionali...

Страница 77: ...oad a bitstream from the CF card image address pointed to by the image select switch S1 With no CF card present the ML605 can be configured via the onboard JTAG controller and USB download cable as de...

Страница 78: ...78 www xilinx com ML605 Hardware User Guide UG534 v1 9 February 26 2019 Chapter 1 ML605 Evaluation Board Send Feedback...

Страница 79: ...CE Mode 1 1 off 3 SysAce CFGAddr 2 0 off 2 SysAce CFGAddr 1 0 off 1 SysAce CFGAddr 0 0 off S2 FPGA mode boot PROM select and FPGA CCLK select 6 pole DIP switch 6 FLASH_A23 0 off 5 M2 0 off 4 M1 1 M 2...

Страница 80: ...o Cu no clk Jump 1 2 J67 pins 1 2 GMII MII to Cu pins 2 3 SGMII to Cu no clk Jump 1 2 J68 J66 pins 1 2 J68 ON RGMII modified MII in Cu no jumper FMC JTAG Bypass J18 exclude FMC LPC connector Jump 1 2...

Страница 81: ...NC NC 14 NC NC LA07_N GND NC NC LA09_P LA10_P NC NC 15 NC NC GND LA12_P NC NC LA09_N LA10_N NC NC 16 NC NC LA11_P LA12_N NC NC GND GND NC NC 17 NC NC LA11_N GND NC NC LA13_P GND NC NC 18 NC NC GND LA...

Страница 82: ...P LA12_N HA15_P HA16_N GND G ND DP 6_M2C_P G ND 17 HA17_N_C C G ND LA11_N GND HA15_N GND LA13_P GND DP6_M2C _N GND 18 G ND HA18_P GND LA16_P GND HA20_P LA13_N LA14_P GND DP5_M2C _P 19 HA21_P HA18_N LA...

Страница 83: ...on board schematic Identify the appropriate pins and replace the net names with net names in the user RTL See the Constraints Guide UG625 Ref 25 for more information The FMC connectors J63 LPC and J64...

Страница 84: ...84 www xilinx com ML605 Hardware User Guide UG534 v1 9 February 26 2019 Appendix C Xilinx Design Constraints Send Feedback...

Страница 85: ...of conformity xtp251 zip CE Directives 2006 95 EC Low Voltage Directive LVD 2004 108 EC Electromagnetic Compatibility EMC Directive CE Standards EN standards are maintained by the European Committee...

Страница 86: ...of life Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer Xilinx has also elected to join WEEE Compliance Schemes in so...

Страница 87: ...IO Resources User Guide 8 UG362 Virtex 6 FPGA User Guide Clocking Resources 9 UG363 Virtex 6 FPGA Memory Resources User Guide 10 UG364 Virtex 6 FPGA Configurable Logic Block User Guide 11 UG365 Virtex...

Страница 88: ...lash Memory Data Sheet TE28F128J3D 75 28 SiTime Oscillator Data Sheet SiT9102AI 243N25E200 00000 29 MMD Components MBH Series Data Sheet MBH2100H 66 000 MHz 30 PCI SIG PCI Express Specifications 31 Ma...

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