
ML40x Getting Started Tutorial
29
UG083 (v5.0) June 30, 2006
ML40x Demonstrations in Linear Flash
R
shows step 1 of the linear flash configuration process when the bitstreams are
uploaded. In this step, the CPU reads *
.bit
files from the CompactFlash and writes them
into linear flash. Up to eight different configurations can be stored in the flash.
shows step 2 of the configuration process, where the FPGA is configured. In this
step, the CPLD (95144XL) reads the flash and configures the FPGA. DIP switches on the
ML40
x
board select which bitstream to download. The FPGA is configured in slave-serial
mode.
Figure 8:
Linear Flash Configuration Process: Step 1
Figure 9:
Linear Flash Configuration Process: Step 2
UG083_06_022805
CompactFlash
Memory
CompactFlash
Interface
CPU
Virtex-4 FPGA
Flash
Interface
Linear
Flash
UG083_07_022805
Linear
Flash
95144XL
CPLD
Virtex-4
FPGA