Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
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UG145 January 18, 2006
SGMII Example Design / Dynamic Switching Example Design
R
VHDL
project_dir>
/
<component_name>
/example_design/
<component_name>_top.vhd
Verilog
project_dir>
/
<component_name>
/example_design/
<component_name>_top.v
The example design HDL top level contains the following:
•
An instance of the Ethernet 1000BASE-X PCS/PMA core in SGMII mode.
•
An instance of a Virtex-II Pro or Virtex-4 RocketIO transceiver.
•
Clock management logic for the core and the RocketIO transceiver, including DCM
and Global Clock Buffer instances.
•
An SGMII adaptation module containing:
-
The clock management logic required to enable the SGMII example design to
operate at 10 Mbps, 100 Mbps, and 1 Gbps
-
GMII logic for both transmitter and receiver paths; the GMII style 8-bit interface is
run at 125 MHz for 1 Gbps operation; 12.5 MHz for 100 Mbps operation; 1.25
MHz for 10 Mbps operation.
•
External GMII logic, including IOB and DDR register instances, where required.
•
Input and output buffers for other port signals of the example design top level.
The example design HDL top-level connects the GMII of the core to the SGMII adaptation
module and the PHY side interface of the core directly to a RocketIO instance. This allows
the functionality of the core to be demonstrated using a simulation package, as described
in this guide.
Transceiver
A wrapper file for the Virtex-II Pro RocketIO or Virtex-4 Multi-Gigabit Transceiver is
described in the following files:
VHDL
project_dir>
/
<component_name>
/example_design/
transceiver.vhd
Verilog
project_dir>
/
<component_name>
/example_design/
transceiver.v
This file instances a Virtex-II Pro RocketIO or Virtex-4 RocketIO and applies Gigabit
Ethernet 1000BASE-X attributes to it. This transceiver wrapper is instantiated from the top-
level HDL file for the example design.
For Virtex-4 FX devices only, a Calibration Block is required. See the
Calibration Block Users
Guide
for more information.
This is decribed in the following files:
VHDL
project_dir/<component_name>/example_design/cal_block_v1_2_1.vhd
Verilog
project_dir/<component_name>/example_design/cal_block_v1_2_1.v
Содержание LogiCORE
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