Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
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21
UG145 January 18, 2006
Implementing the Example Design
R
The default core and its supporting files, including the example design, are generated in
your project directly. For a detailed description of the design example files and directories,
refer to
“Directory Structure and File Descriptions” in Chapter 4
.
Implementing the Example Design
Note:
Available only with a Full license.
After the core is generated, the netlists and example design can be processed by the Xilinx
implementation tools. The generated output files include several scripts to assist you in
running the Xilinx software.
To implement the Ethernet 1000BASE-X PCS/PMA or SGMII sample design core
From the CORE Generator project directory window, type in the following:
For UNIX:
unix-shell>
cd <project_dir>/<component_name>/implement
unix-shell>
./implement.sh
For Windows:
ms-dos>
cd <project_dir>\<component_name>\implement
ms-dos>
implement.bat
These commands execute a script that synthesizes, builds, maps, and place-and-routes the
example design. The script then creates gate-level netlist HDL files in either VHDL or
Verilog, along with associated timing information (SDF) files.
Simulating the Example Design
Setting up for Simulation
To run the gate-level simulation you must have the Xilinx Simulation Libraries compiled
for your system. See the Compiling Xilinx Simulation Libraries (COMPXLIB) in the
Xilinx
ISE Synthesis and Verification Design Guide
, and the
Xilinx ISE Software Manuals and Help
.
You can download these documents from:
http://www.xilinx.com/support/software_manuals.htm
.
In addition, the simulator you use must provide SWIFT model support to simulate the
Virtex-II Pro or Virtex-4 RocketIO
TM
transceivers.
In the simulation examples that follow,
<project_dir>
is the CORE Generator project
directory;
<component_name>
is the component name as entered in the core customization
window.
Functional Simulation
Note:
Available for both license types.
This section provides instructions for running a functional simulation or the Ethernet
1000BASE-X PCS/PMA or SGMII core using either VHDL or Verilog. The functional
simulation model is provided when the core generated; implementing the core before
simulation is not required.
Содержание LogiCORE
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