Xilinx LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1, Руководство пользователя

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UG155 March 24, 2008
Clock Sharing - Multiple Cores with RocketIO, Fabric Elastic Buffer
R
Virtex-5 LXT and SXT Devices
Figure 8-9 illustrates sharing clock resources across multiple instantiations of the core
when using the Virtex-5 RocketIO GTP transceiver. The example design can be generated
to connect either a single instance of the core, or connect a pair of core instances to the
transceiver pair present in a GTP transceiver tile.
Figure 8-9 illustrates two instantiations of
the block level, and each block level contains a pair of cores. Figure 8-9 illustrates clock
sharing between four cores.
More cores can be added by instantiating extra block level modules. Share the
brefclk_p
and
brefclk_n
differential clock pairs. See the Virtex-5 RocketIO GTP Transceiver User
Guide for more information.
To provide the 125 MHz clock for all core instances, select a
REFCLKOUT
port from any
GTP transceiver. This can be routed onto global clock routing using a BUFG as illustrated
and shared between all cores and GTP transceivers in the column.
Each GTP and core pair instantiated has its own independent clock domains synchronous
to
RXRECCLK0
and
RXRECCLK1
. These are placed on regional clock routing using a BUFR,
as illustrated in Figure 8-9 , and cannot be shared across multiple GTP transceivers.