Xilinx LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1, Руководство пользователя

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Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 109
UG155 March 24, 2008
Clock Sharing - Multiple Cores with RocketIO, Fabric Elastic Buffer
R
Virtex-4 FX Devices
Figure 8-8 illustrates sharing clock resources across multiple instantiations of the core
when using the Virtex-4 RocketIO MGT. Note that the example design, when using the
Virtex-4 family, can be generated to connect either a single instance of the core, or connect
a pair of core instances to the transceiver pair present in a MGT tile.
Figure 8-8 illustrates
two instantiations of the block level, and each block level contains a pair of cores,
illustrating clock sharing between four cores.
More cores can be added by continuing to instantiate extra block level modules. Share
clocks only between the MGTs in a single column. For each column, use a single
brefclk_p
and
brefclk_n
differential clock pair and connect this to a
GT11CLK_MGT
primitive. The clock output from this primitive should be shared across all used MGT tiles
in the column. See the
Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide for more
information.
To provide the 125 MHz clock for all core instances, select a
TXOUTCLK1
port from any
MGT. This can be routed onto global clock routing using a BUFG as illustrated, and shared
between all cores and MGTs in the column.
Each MGT and core pair instantiated has its own independent clock domain synchronous
to
RXRECCLK1
which is placed on regional clock routing using a BUFR, as illustrated in
Figure 8-8 –these cannot be shared across multiple MGTs. Although not illustrated in
Figure 8-8 ,
dclk
(the clock used for the calibration blocks and for the Dynamic
Reconfiguration Port (DRP) of the MGTs) can also be shared.