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Power Management

To power the K26 SOM, it is recommended that you split the power system on your carrier card
is into three power domains:

• Always On Power Domain: The +5V main power and auxiliary power support infrastructure

components such as the power management and telemetry circuits, reset circuits, and
clocking circuits.

• PS Power Domain: The power rails that support the peripherals connected to the PS MIO and

PS-GTR signals.

• PL Power Domain: The power rails that support the peripherals connected to the PL HDIO

and HPIO signals and the V

CCO

rails.

Power Sequencing

The carrier card power management circuit for your application must use the following sequence
to power on the K26 SOM. Your carrier card supplies the +5V SOM power rail (V

CC_SOM

).

1. When the V

CC_SOM

voltage level is within the specified range, the carrier card deasserts the

POWER_OFF_C2M_L signal.

2. The K26 SOM initiates onboard power sequencing.

3. The K26 SOM asserts the VCCOEN_PS_M2C signal, indicating to the carrier card to turn on

the supply rails for the PS peripheral devices.

4. The K26 SOM asserts the VCCOEN_PL_M2C signal, indicating to the carrier card to turn on

the supply rails for the PL peripheral devices as well as all V

CCO

rails for the HPIO and HDIO

banks.

Power Telemetry

RECOMMENDED: Your carrier card should employ a current sensing device to monitor the input current
on the V

CC_SOM

supply rail that is powering the SOM. Xilinx carrier cards add this current sensing device to

the PS I2C bus to minimize I/O.

Chapter 2: Electrical Design Considerations

UG1091 (v1.0) April 20, 2021

Carrier Card Design for Kria SOM

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Содержание Kria K26 SOM

Страница 1: ...Kria SOM Carrier Card Design Guide UG1091 v1 0 April 20 2021 ...

Страница 2: ...ing table shows the revision history for this document Section Revision Summary 4 20 2021 Version 1 0 Initial release N A Revision History UG1091 v1 0 April 20 2021 www xilinx com Carrier Card Design for Kria SOM 2 Send Feedback ...

Страница 3: ...acement Guidelines 40 Carrier Card Board to Board Connector Placement Guideline 41 Recommended Pb free Reflow Soldering Profile 47 Carrier Card to SOM Standoff Press fit Process 49 Board to Board Assembly Guidelines 50 Mating JSOM Standoff nut Tighten Sequence and Torque Setup 52 De mating JSOM Standoff nut and Jack Screw Untighten Sequence 53 SOM System B2B Connector Assembly Validation DOE To En...

Страница 4: ...linx Resources 57 Documentation Navigator and Design Hubs 57 References 57 Please Read Important Legal Notices 58 UG1091 v1 0 April 20 2021 www xilinx com Carrier Card Design for Kria SOM 4 Send Feedback ...

Страница 5: ...tible carrier card The document is not intended to be self contained meaning that there are references to other Xilinx product documentation to help the reader find more detailed technical information available in corresponding technical reference manuals software design guides and thermal design guides The Kria K26 SOM is used an example throughout the guide and is shown in the following block di...

Страница 6: ...2_FPD S_AXI_HP1_FPD S_AXI_HP0_FPD S_AXI_ACP_FPD S_AXI_ACE_FPD S_AXI_HPC0_FPD S_AXI_HPC1_FPD M_AXI_HPM0_FPD M_AXI_HPM1_FPD I O Coherent Master GPU CFG LPD Main Switch RPU Switch Full crossbar Each input to all output ports Full crossbar To all output ports GPIO x78 x96 FPD Main Switch AXI Stream SIOU Outbound APB Non Coherent Master RPU M M TTC x4 LPD SWDT M M TBU3 TBU4 TBU1 TBU0 VCU RF PCIe v3 1 1...

Страница 7: ...Rate HD high density 4 row 60 position connector set The part number for the socket ADF6 60 03 5 L 4 2 A is used on the bottom side of the SOM The part number for the terminal ADM6 60 01 5 L 4 2 A is for use on the carrier card The SOM240_1 and SOM240_2 connectors provide support for following interfaces Control and status signals Multiplexed I O MIO bank PS GTR high speed serial transceiver signa...

Страница 8: ... to indicate an active Low signal Table 2 Legend for Connector Pinouts Example SOM240 Connector Function GND Both SOM240_1 and SOM240_2 Ground pins VCC_SOM Both SOM240_1 and SOM240_2 Power connection pins MIO35 SOM240_1 MIO 501 bank pins MIO58 SOM240_1 MIO 502 bank pins JTAG_TMS_C2M SOM240_1 Configuration and control pins GTR_DP1_M2C_P SOM240_1 PS GTR transceiver pins HPA04_P SOM240_1 HPA pins HDA...

Страница 9: ...D HDA05 HDA06 HDA02 19 VCCOEN_PS_M2C GND HDA07 GND 20 VCCOEN_PL_M2C HDA15 HDA08_CC HDA12 21 GND HDA16_CC GND HDA13 22 JTAG_TMS_C2M HDA17 HDA18 HDA14 23 JTAG_TDO_M2C GND HDA19 GND 24 JTAG_TDI_C2M PS_ERROR_OUT_M2C HDA20 PWRGD_FPD_M2C 25 JTAG_TCK_C2M PS_ERROR_STATUS_M2C GND PWRGD_LPD_M2C 26 GND PWROFF_C2M_L MIO24_I2C_SCK PWRGD_PL_M2C 27 MODE0_C2M GND MIO25_I2C_SDA GND 28 MODE1_C2M MIO35 MIO12_FWUEN_C...

Страница 10: ... GTR_DP2_C2M_N GND GTR_REFCLK2_C2M_N 55 GTR_DP0_C2M_P GND GTR_DP1_C2M_P GND 56 GTR_DP0_C2M_N GND GTR_DP1_C2M_N GND 57 GND GTR_DP0_M2C_P GND GTR_DP2_M2C_P 58 GND GTR_DP0_M2C_N GND GTR_DP2_M2C_N 59 VCC_SOM GND VCC_SOM GND 60 VCC_SOM VCC_SOM VCC_SOM VCC_SOM SOM240_1 Signal Names and Descriptions Table 4 SOM240_1 Signal Pins Pin Number Signal Name Signal Description Connector Row A A1 VCC_BATT PS BBRA...

Страница 11: ...A25 JTAG_TCK_C2M JTAG clock pulled up at 1 8V on the SOM A26 GND Ground A27 MODE0_C2M PS mode bit 0 pulled up at 1 8V on the SOM A28 MODE1_C2M PS mode bit 1 pulled up at 1 8V on the SOM A29 MODE2_C2M PS mode bit 2 pulled up at 1 8V on the SOM A30 MODE3_C2M PS mode bit 3 pulled up at 1 8V on the SOM A31 Reserved No connect on the SOM A32 Reserved No connect on the SOM A33 GND Ground A34 MIO41 PS MI...

Страница 12: ...PIO clock capable pin on bank 66 B3 GND Ground B4 HPA04_P HPIO on bank 66 B5 HPA04_N HPIO on bank 66 B6 GND Ground B7 HPA07_P HPIO on bank 66 B8 HPA07_N HPIO on bank 66 B9 GND Ground B10 HPA11_P HPIO on bank 66 B11 HPA11_N HPIO on bank 66 B12 GND Ground B13 VCCO_HDA HDA I O voltage rail 1 2V to 3 3V B14 VCCO_HDA HDA I O voltage rail 1 2V to 3 3V B15 GND Ground B16 HDA03 HDIO on bank 45 B17 HDA04 H...

Страница 13: ...ctor B39 GND Ground B40 MIO58 PS MIO signal on bank 502 B41 MIO59 PS MIO signal on bank 502 B42 MIO60 PS MIO signal on bank 502 B43 GND Ground B44 MIO70 PS MIO signal on bank 502 B45 MIO71 PS MIO signal on bank 502 B46 MIO72 PS MIO signal on bank 502 B47 GND Ground B48 GND Ground B49 GTR_REFCLK1_C2M_P PS GTR REFCLK1 input B50 GTR_REFCLK1_C2M_N PS GTR REFCLK1 input B51 GND Ground B52 GND Ground B53...

Страница 14: ...DIO on bank 45 C20 HDA08_CC HDIO clock capable pin on bank 45 C21 GND Ground C22 HDA18 HDIO on bank 45 C23 HDA19 HDIO on bank 45 C24 HDA20 HDIO on bank 45 C25 GND Ground C26 MIO24_I2C_SCK PS I2C clock output C27 MIO25_I2C_SDA PS I2C serial data C28 MIO12_FWUEN_C2M_L Firmware user enable indication C29 GND Ground C30 MIO29 PS MIO signal on bank 501 No connect on the SOM C31 MIO30 PS MIO signal on b...

Страница 15: ...P1_C2M_N PS GTR lane 1 RX C57 GND Ground C58 GND Ground C59 VCC_SOM SOM main supply voltage 5V C60 VCC_SOM SOM main supply voltage 5V Connector Row D D1 VCCO_HPA HPA I O voltage rail 1 0V to 1 8V D2 VCCO_HPA HPA I O voltage rail 1 0V to 1 8V D3 GND Ground D4 HPA02_P HPIO on bank 66 D5 HPA02_N HPIO on bank 66 D6 GND Ground D7 HPA01_P HPIO on bank 66 D8 HPA01_N HPIO on bank 66 D9 GND Ground D10 HPA0...

Страница 16: ...gnal on bank 501 D33 MIO45 PS MIO signal on bank 501 D34 MIO46 PS MIO signal on bank 501 D35 GND Ground D36 MIO52 PS MIO signal on bank 502 D37 MIO53 PS MIO signal on bank 502 D38 MIO54 PS MIO signal on bank 502 D39 GND Ground D40 MIO64 PS MIO signal on bank 502 D41 MIO65 PS MIO signal on bank 502 D42 MIO66 PS MIO signal on bank 502 D43 GND Ground D44 MIO76 PS MIO signal on bank 502 D45 MIO77 PS M...

Страница 17: ...ND 5 GND GTH_DP2_M2C_P GND GTH_DP3_M2C_P 6 GND GTH_DP2_M2C_N GND GTH_DP3_M2C_N 7 GTH_REFCLK1_C2M_P GND GTH_DP1_M2C_P GND 8 GTH_REFCLK1_C2M_N GND GTH_DP1_M2C_N GND 9 GND GTH_DP0_C2M_P GND GTH_DP0_M2C_P 10 GND GTH_DP0_C2M_N GND GTH_DP0_M2C_N 11 HPB15_CC_P GND HPB09_P GND 12 HPB15_CC_N HPB10_CC_P HPB09_N HPB01_P 13 GND HPB10_CC_N GND HPB01_N 14 HPB08_P GND HPB14_P GND 15 HPB08_N HPB07_P HPB14_N HPB00...

Страница 18: ...C15_CC_N HPC18_P HPC12_N HPC04_P 40 GND HPC18_N GND HPC04_N 41 HPC03_P GND HPC_CLK0_P GND 42 HPC03_N VCCO_HPB HPC_CLK0_N VCCO_HPC 43 GND GND GND GND 44 VCCO_HPB HDB12 VCCO_HPC HDB00_CC 45 GND HDB13 GND HDB01 46 HDB18 HDB14 HDB06 HDB02 47 HDB19 GND HDB07 GND 48 HDB20 HDB15 HDB08_CC HDB03 49 GND HDB16_CC GND HDB04 50 HDB21 HDB17 HDB09 HDB05 51 HDB22 GND HDB10 GND 52 HDB23 HDC12 HDB11 HDC00_CC 53 GND...

Страница 19: ... HPIO on bank 65 A15 HPB08_N HPIO on bank 65 A16 GND Ground A17 HPB12_P HPIO on bank 65 A18 HPB12_N HPIO on bank 65 A19 GND Ground A20 HPB06_P HPIO on bank 65 A21 HPB06_N HPIO on bank 65 A22 GND Ground A23 HPB16_P HPIO on bank 65 A24 HPB16_N HPIO on bank 65 A25 GND Ground A26 HPB_19_P HPIO on bank 65 A27 HPB_19_N HPIO on bank 65 A28 GND Ground A29 HPC08_P HPIO on bank 64 A30 HPC08_N HPIO on bank 6...

Страница 20: ...DB23 HDIO on bank 43 A53 GND Ground A54 HDC18 HDIO on bank 44 A55 HDC19 HDIO on bank 44 A56 HDC20 HDIO on bank 44 A57 GND Ground A58 HDC21 HDIO on bank 44 A59 HDC22 HDIO on bank 44 A60 HDC23 HDIO on bank 44 Connector Row B B1 GTH_DP2_C2M_P GTH Lane 2 RX B2 GTH_DP2_C2M_N GTH Lane 2 RX B3 GND Ground B4 GND Ground B5 GTH_DP2_M2C_P GTH Lane 2 TX B6 GTH_DP2_M2C_N GTH Lane 2 TX B7 GND Ground B8 GND Grou...

Страница 21: ... HPC13_N HPIO on bank 64 B32 GND Ground B33 HPC16_P HPIO on bank 64 B34 HPC16_N HPIO on bank 64 B35 GND Ground B36 HPC07_P HPIO on bank 64 B37 HPC07_N HPIO on bank 64 B38 GND Ground B39 HPC18_P HPIO on bank 64 B40 HPC18_N HPIO on bank 64 B41 GND Ground B42 VCCO_HPB HPB I O voltage rail 1 0V to 1 8V B43 GND Ground B44 HDB12 HDIO on bank 43 B45 HDB13 HDIO on bank 43 B46 HDB14 HDIO on bank 43 B47 GND...

Страница 22: ... Lane 1 TX C9 GND Ground C10 GND Ground C11 HPB09_P HPIO on bank 65 C12 HPB09_N HPIO on bank 65 C13 GND Ground C14 HPB14_P HPIO on bank 65 C15 HPB14_N HPIO on bank 65 C16 GND Ground C17 HPB02_P HPIO on bank 65 C18 HPB02_N HPIO on bank 65 C19 GND Ground C20 HPB13_P HPIO on bank 65 C21 HPB13_N HPIO on bank 65 C22 GND Ground C23 HPB_18_P HPIO on bank 65 C24 HPB_18_N HPIO on bank 65 C25 GND Ground C26...

Страница 23: ...C47 HDB07 HDIO on bank 43 C48 HDB08_CC HDIO clock capable pin on bank 43 C49 GND Ground C50 HDB09 HDIO on bank 43 C51 HDB10 HDIO on bank 43 C52 HDB11 HDIO on bank 43 C53 GND Ground C54 HDC06 HDIO on bank 44 C55 HDC07 HDIO on bank 44 C56 HDC08_CC HDIO clock capable pin on bank 44 C57 GND Ground C58 HDC09 HDIO on bank 44 C59 HDC10 HDIO on bank 44 C60 HDC11 HDIO on bank 44 Connector Row D D1 GTH_DP1_...

Страница 24: ...7 HPC09_P HPIO on bank 64 D28 HPC09_N HPIO on bank 64 D29 GND Ground D30 HPC01_P HPIO on bank 64 D31 HPC01_N HPIO on bank 64 D32 GND Ground D33 HPC00_CC_P HPIO clock capable pin on bank 64 D34 HPC00_CC_N HPIO clock capable pin on bank 64 D35 GND Ground D36 HPC02_P HPIO on bank 64 D37 HPC02_N HPIO on bank 64 D38 GND Ground D39 HPC04_P HPIO on bank 64 D40 HPC04_N HPIO on bank 64 D41 GND Ground D42 V...

Страница 25: ...re a reference voltage VREF For more information refer to the UltraScale Architecture SelectIO Resources User Guide UG571 Signal Routing Guidelines This section provides signal routing guidelines and required PCB layout constraints for all interfaces provided on the SOM Note Consult the UltraScale Architecture PCB Design User Guide UG583 for detailed information MIO Signals Route all MIO signals M...

Страница 26: ...distance between signal to nearest GND plane Match other application specific HPIO use cases per the HPIO signal group interface requirement PS GTR Transceivers PS GTR transceivers support a maximum transfer rate of 6 Gb s over each lane To minimize the impedance discontinuity at the SOM connector interface route the PS GTR signals using a 90Ω differential impedance Match P and N differential sign...

Страница 27: ...to the nearest GND plane Reference Clocks Both the PS GTR and PL GTH transceivers differential clock signals REFCLKs must meet following signal integrity requirements The target differential impedance of 100Ω Match P and N differential signals to within 0 5 mils of each other REFCLK to all other signal spacing should be five times the distance between the signal to the nearest GND plane I O Constr...

Страница 28: ...slew rate For I O modeling including drive strength settings the Zynq UltraScale MPSoC IBIS models can be downloaded from the Xilinx website SOM Configuration and Control Signals This section outlines the configuration and control signals associated with managing the Zynq UltraScale MPSoC SOM Power on Reset PS_POR_B Signal This is the Zynq UltraScale MPSoC power on reset signal In Xilinx documenta...

Страница 29: ...asserted when there is an accidental loss of power a hardware error or an exception in the PMU For secure scenarios where device status is disabled from external visibility there are PMU control registers to mask PS_ERROR_OUT For more information see the Zynq UltraScale Device Technical Reference Manual UG1085 PS_ERROR_STATUS indicates a secure lockdown state Alternatively it can be used by the PM...

Страница 30: ...on to reset the system at any time PS_SRST_C2M_L The PS_SRST_C2M_L pin connects to PS_SRST_B signal on the SOM Zynq UltraScale MPSoC PS_SRST_B input signal to the Zynq UltraScale MPSoC is the system reset signal and it is commonly used during debug PS_SRST_C2M_L is pulled High to 1 8V on the SOM Power Management Signals PWROFF_ C2M_L PWROFF_C2M_L is an active Low signal to power down the SOM and p...

Страница 31: ...PWRGD_PL_M2C is pulled High to 1 80V on the SOM A carrier card can use this signal to monitor PL power status VCCOEN_PS_M2C VCCOEN_PS_M2C is an active High output signal from the SOM power system to enable the PS VCCO rails that are supplied by the carrier card A carrier card can use this signal as an indication to turn power on for all PS peripherals VCCOEN_PL_M2C VCCOEN_PL_M2C is an active High ...

Страница 32: ... defined by the physical SOM design and cannot be modified by carrier card designers It defines the MIO configuration for the SOM peripherals QSPI TPM SPI LEDs eMCC and I2C configuration bus Bank 500 MIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Peripheral QSPI SPI1 GPIO0 SPI1 GPIO0 eMMC SD0 GPIO0 I2C1 Pin Fct sclk_out miso_mo1 mo2 mo3 mosi_mi0 n_ss_out sclk_out LED0 LED1...

Страница 33: ...t MIO31 PMU input pin External watchdog toggle MIO35 PMU output pin MIO Bank 501 UART RECOMMENDED The carrier card design should include a UART for board bring up and initial debug The Xilinx K26 boot firmware and PetaLinux BSP default the UART interface to MIO36 and MIO37 It is recommended that carrier card designs use this same mapping to be able to use the Xilinx provided software references Ba...

Страница 34: ...p maximum noise 4A Main power input to the SOM Supplies power to on board power regulators VCC_BATT 1 50V External battery input for the RTC VCCO_HPA 1 00V 1 80V 1 0A Voltage rail for HPIO bank 66 VCCO_HPB 1 00V 1 80V 1 0A Voltage rail for HPIO bank 65 VCCO_HPC 1 00V 1 80V 1 0A Voltage rail for HPIO bank 64 VCCO_HDA 1 20V 3 30V 1 0A Voltage rail for HDIO bank 45 VCCO_HDB 1 20V 3 30V 1 0A Voltage r...

Страница 35: ...s the 5V SOM power rail VCC_SOM 1 When the VCC_SOM voltage level is within the specified range the carrier card deasserts the POWER_OFF_C2M_L signal 2 The K26 SOM initiates onboard power sequencing 3 The K26 SOM asserts the VCCOEN_PS_M2C signal indicating to the carrier card to turn on the supply rails for the PS peripheral devices 4 The K26 SOM asserts the VCCOEN_PL_M2C signal indicating to the c...

Страница 36: ...Hub The SYSMON is supported for bare metal applications by the SYSMONPSU driver SOM Power Integrity The K26 SOM is equipped with adequate decoupling capacitors on all PS and PL voltage rails to support a defined set of transient step loads The programmable logic PL and processing system PS designs must not exceed the specified maximum current limit and the corresponding step loads as listed in the...

Страница 37: ...SOM The following mechanical drawing provides the detailed dimensions of the SOM Table 13 K26 SOM Mechanical Specifications Parameter Specification SOM length 77 mm SOM width 60 mm SOM height 10 9 mm Mass 58 grams Chapter 3 Mechanical Design Considerations UG1091 v1 0 April 20 2021 www xilinx com Carrier Card Design for Kria SOM 37 Send Feedback ...

Страница 38: ...Figure 2 K26 SOM Dimensions Chapter 3 Mechanical Design Considerations UG1091 v1 0 April 20 2021 www xilinx com Carrier Card Design for Kria SOM 38 Send Feedback ...

Страница 39: ...to pad and component placement tolerance based on the capabilities listed above should be 36 µm Samtec recommends a tolerance of 0 04 mm in the distance between the connectors The combination of the all these requirements must be controlled to less than 40 µm The evaluation of Samtec connector placement is conducted by shifting the placement of the connector from 0 PCB pad center aligned with conn...

Страница 40: ...er card centered between the mounting holes shown in Figure 2 K26 SOM Dimensions Board to board B2B mating connectors must be precisely placed on the PCB particularly for multi pair connector applications Tight control is required during the board layout design and the manufacturing process for product reliability and a decent yield rate To avoid over stressing the mechanical design of the connect...

Страница 41: ... your carrier card The two SOM mating connectors must be placed and positioned using a tightly controlled design and manufacture processing The following figure shows the keep out area and connector position tolerance information used on an example carrier card design The keep out area defined maximum component height is 1 0 mm Chapter 3 Mechanical Design Considerations UG1091 v1 0 April 20 2021 w...

Страница 42: ...Figure 4 Carrier Card Board to Board Connector Placement Tolerances Chapter 3 Mechanical Design Considerations UG1091 v1 0 April 20 2021 www xilinx com Carrier Card Design for Kria SOM 42 Send Feedback ...

Страница 43: ...and was validated through dye and pry where the sample passed Figure 5 Recommended Locations for Strain Measurement on a Carrier Card Board to Board Connector Distance Tolerance Control The distance between the mating ADM6 connectors on the carrier card must match the distance between the ADF6 connectors on the SOM The final connector position is dictated by auto placement machine accuracy and PCB...

Страница 44: ...D Distance D should be 66 612 mm nominal The allowable distance D and tolerance is 66 612 0 04 mm center to center The following table shows the recommended optical measurement instrument specifications Name OGP Smartscope Model CNC670 Accuracy 5 μm Figure 6 Connector Distance Measurement Chapter 3 Mechanical Design Considerations UG1091 v1 0 April 20 2021 www xilinx com Carrier Card Design for Kr...

Страница 45: ...ollowing figure is recommended for better reliability performance Figure 7 Recommended PCB Layout for Board to Board Connector Board to Board Connector Pad Placement The following figure outlines the carrier card connector pads and mechanical standoff relative placement Chapter 3 Mechanical Design Considerations UG1091 v1 0 April 20 2021 www xilinx com Carrier Card Design for Kria SOM 45 Send Feed...

Страница 46: ...ases the thickness of a stencil must be matched to the needs of all components on the PCB Stencil apertures should be a circular shape A laser cutting mostly made from stainless steel with nickel blanking is preferred to ensure that both uniform and high solder paste is transferred to the PCB The recommended stencil design dimensions are listed in the following table and shown in the image Chapter...

Страница 47: ...itional Sn Pb soldering processes have a peak reflow temperature of 220 C At this temperature range the SnAgCu BGA solder balls cannot properly melt and wet to the soldering surfaces As a result reliability and assembly yields can be compromised The optimal profile must take a few factors into account Solder paste flux used Size of the board Density of the components on the board Ratio of large an...

Страница 48: ...mperature of 235 C for at least 10 seconds Reflowing at high peak temperatures of 260 C or above can damage the heat sensitive components and cause board warpage Refer to the latest IPC JEDEC J STD 020 standard for allowable peak temperature on the components The allowable component peak temperature is determined by the component size The following table lists the reflow soldering temperature prof...

Страница 49: ...rocess to install them onto the PCB The JSOM standoff press fit recommended parameters are shown the following table and the press profile is shown in the following diagram Table 17 JSOM Standoff Press fit Parameters Press Parameter Setting Unit Press Time Force 350 10 lbs 2 secs Figure 11 Press Profile Force Over Time The following images detail the installation process by using a press fit jig C...

Страница 50: ...the top tool once the press fit is completed 4 Repeat step 3 to install the JSOM standoff located beside connector JA1 Remove the board from the jig and inspect whether the JSOM standoff is fully flush Board to Board Assembly Guidelines Samtec jack screw standoff part number JSOM 0515 01 is recommended by Samtec to be used as mechanical support in its board to board B2B connector assembly This JSO...

Страница 51: ...5311 041621 A recommended best practice is to put board to board alignment arrows on your carrier card silkscreen to aid in the orientation of the SOM to carrier card It is important to check the connector alignment key positions before gently pressing down to fully engage the B2B connectors Chapter 3 Mechanical Design Considerations UG1091 v1 0 April 20 2021 www xilinx com Carrier Card Design for...

Страница 52: ...rtant to tighten the standoff nut in a specific sequence The recommended mechanical standoff tightening sequence S W N E is shown in the following figure Once the S and W nuts are tightened the SOM board will be almost flat to the carrier card The subsequent tightening of nuts N and E ensure the SOM and carrier connectors are completely engaged Chapter 3 Mechanical Design Considerations UG1091 v1 ...

Страница 53: ...Standoff nut and Jack Screw Untighten Sequence There is no special sequence required to untighten the four standoff nuts However they must be removed before proceeding to untighten the four jack screws The order to untighten the four jack screws is not critical Once all four of the jack screws are completely untightened the SOM board will pop up and the SOM connectors male automatically uncouple f...

Страница 54: ...ion testing to validate their mating conditions Based on the cross section images the connectors which shifted by 15 were able to self align during reflow soldering The following photos are a cross section image of the mated connectors The proper contact of the female and male connector pins is achieved Figure 16 Cross section Image of Mated Connectors for 0 Shift Figure 17 Cross section Image of ...

Страница 55: ...PI non volatile memory and associated clocking eMMC non volatile memory and associated clocking SPI interface for a trusted platform module TPM I2C peripheral bus for SOM peripherals and extensible via carrier card design UART for board bring up and software debug assumes the carrier card pins out MIO36 and MIO37 for proper UART function PMU input output need to check default board file configurat...

Страница 56: ...rd constraints file can be described in terms of a SOM physical interface when combined with a SOM constraint file that captures the Zynq UltraScale MPSoC to SOM connector pin definition SOM Vivado Tools XDC Files The SOM Vivado board file includes an XDC file that captures the Zynq UltraScale MPSoC package mapping to SOM connector pin definitions This file can be used by the carrier card designer...

Страница 57: ...ilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics which you can use to learn key concepts and address frequently asked questions To access the Design Hubs In DocNav click the Design Hubs View tab On the Xilinx website see the Design Hubs page Note For more information on DocNav see the Doc...

Страница 58: ...s including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Ma...

Страница 59: ...REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY Copyright Copyright 2021 Xilinx Inc Xilinx the Xilinx logo Alveo Artix Kintex Spartan Versal Virtex Vivado Zynq and other designated brands included herein are trademarks of Xilinx in the United States and other countries AMBA AMBA Designer Arm ARM1176JZ S CoreSight Cortex PrimeCell Mali and MPCore are trademarks of Arm Limited in the EU and o...

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