FPGA Video Processing Development Platform AV6045 User Manual
6 / 54
Contact Email: [email protected]
Part 1: FPGA Development Board Introduction
The entire structure of the AV6045 FPGA development board is inherited
from our consistent core board + carrier board mode. A high-speed inter-board
connector is used between the core board and the carrier board.
The core board is mainly composed of FPGA+ DDR3+ FLASH. It
undertakes the core algorithm of video image processing, fully utilizes the
parallel processing capability of FPGA, and the high-speed data reading and
writing between FPGA and DDR3. The bandwidth of the whole system is up to
10Gb/s (666M*). 16bit); In addition, DDR3 capacity is up to 2Gbit, which meets
the need for high buffers during video processing. The selected FPGA is the
high-speed FPGA chip of XC6SLX45-2FG484 of XILINX SPARTAN6 series.
The FPGA is packaged in BGA 484. SPARTAN6 FPGA integrated DDR
controller hard core, and DDR3 communication clock frequency reached
333Mhz, DDR3 internal 666Mhz, fully meet the needs of four 1080p video
processing.
