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FPGA Video Processing Development Platform AV6045 User Manual

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Contact Email: [email protected]

Video Input Interface Pin Assignment

Pin Name

FPGA Pin

2867_CLKP

C11

2867_CLKN

A11

2867_D[0]

A3

2867_D[1]

C5

2867_D[2]

A4

2867_D[3]

A5

2867_D[4]

D6

2867_D[5]

B6

2867_D[6]

C6

2867_D[7]

A6

Part 4.6: Gigabit Ethernet Interface

The FPGA development board provides users with network

communication services through the Realtek RTL8211EG Ethernet PHY chip.
The RTL8211EG chip supports 10/100/1000 Mbps network transmission rate
and communicates with the FPGA through the GMII interface. RTL8211EG
supports MDI/MDX adaptive, various speed adaptations, Master/Slave
adaptation, and support for MDIO bus for PHY register management.

The RTL8211EG will detect the level status of some specific IOs to

determine their working mode after powered on. Table 4-6-1 describes the
default setup information after the GPHY chip is powered on.

Configuration Pin

Instructions

Configuration value

PHYAD[2:0]

MDIO/MDC Mode PHY Address

PHY Address 011

SELRGV

3.3V, 2.5V, 1.5/1.8V voltage selection

3.3V

AN[1:0]

Auto-negotiation configuration

(10/100/1000M) adaptive

RX Delay

RX clock 2ns delay

Delay

TX Delay

TX clock 2ns delay

Delay

Mode

RGMII or GMII selection

RGMII

Table 4-6-1: PHY chip default configuration value

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Содержание AV6045

Страница 1: ...FPGA Video Processing Development Platform AV6045 User Manual...

Страница 2: ...PGA Video Processing Development Platform AV6045 User Manual 2 54 Contact Email rachel zhou alinx com cn Version Record Version Date Release By Description Rev 1 0 2019 05 01 Rachel Zhou First Release...

Страница 3: ...h 15 Part 3 4 AV6045 Power Supply 17 Part 3 5 Expansion Ports 19 Part 3 6 Powe interface on Core Board 22 Part 3 7 Crystal oscillator on Core Board 23 Part 3 8 LED Light on Core Board 25 Part 3 9 Stru...

Страница 4: ...FPGA Video Processing Development Platform AV6045 User Manual 4 54 Contact Email rachel zhou alinx com cn Part 4 11 Buttons 51 Part 4 12 Power Supply 52...

Страница 5: ...nt board In terms of hardware design we added HDMI input DVI output Gigabit Ethernet CMOS Camera interface and Micro in the original design Peripherals such as SD card slot This greatly enriches the f...

Страница 6: ...core algorithm of video image processing fully utilizes the parallel processing capability of FPGA and the high speed data reading and writing between FPGA and DDR3 The bandwidth of the whole system i...

Страница 7: ...his diagram you can see the interfaces and functions that the AV6045 FPGA Development Board contains 4 channel video input Select Techwell TW2867 can input 4 composite video signals PAL NTSC SECAM aut...

Страница 8: ...communication services to users The RTL8211EG chip supports 10 100 1000 Mbps network transmission rate 1 channel CMOS Input CMOS camera interface can be connected to ALINX s 300 000 pixel OV7670 came...

Страница 9: ...e four channel surveillance camera through the display VGA DVI HDMI interface which can realize 1080p for split screen display Our development board is equivalent to the digital video host in the Figu...

Страница 10: ...Contact Email rachel zhou alinx com cn Figure 2 1 2 Set top box 3 Camera Module CMOS camera interface plug in ALINX 30 megapixel camera module or 5 megapixel camera module real time display 1080P vid...

Страница 11: ...monitors or TV to display HDMI video signals The video display for VGA and HDMI output is up to 1080P 60Hz Current computer monitors basically support one of VGA or HDMI inputs As long as one of the V...

Страница 12: ...FPGA Video Processing Development Platform AV6045 User Manual 12 54 Contact Email rachel zhou alinx com cn Part 3 AC6045 core board...

Страница 13: ...s MT41J128M16LA 187E DDR3 chip with a capacity of 2Gbit 16bit bus mode read and write data bandwidth between FPGA and DDR3 is up to 10Gb this configuration can meet the needs of 4 channels of 1080p v...

Страница 14: ...he normal operation of DDR3 requires DDR3 address line and control line to provide termination voltage VTT and DDR3 chip reference voltage VREF VTT and VREF voltage are both 1 5V the following Figure...

Страница 15: ...DDR3_nCAS K4 DDR3_A 8 E3 DDR3_CKE D2 DDR3_A 9 E1 DDR3_CLK_P H4 DDR3_A 10 G4 DDR3_CLK_N H3 DDR3_nRAS K5 DDR3_DQ 8 P2 DDR3_nWE F2 DDR3_DQ 9 P1 DDR3_ODT J6 DDR3_DQ 10 R3 DDR3_RESET C3 DDR3_DQ 11 R1 DDR3...

Страница 16: ...system to store the boot image of the system These images mainly include FPGA bit files core application code and other user data files The specific models and related parameters of SPI FLASH are show...

Страница 17: ...l not be repeated here The VCCO of the FPGA is separated from the VCCAUX power supply The purpose is to enable the BANK IO voltage of the FPGA to be flexibly adjusted Different output voltages are obt...

Страница 18: ...FPGA Video Processing Development Platform AV6045 User Manual 18 54 Contact Email rachel zhou alinx com cn Figure 3 4 1 Power Supply on core board schematic...

Страница 19: ...has a total of two high speed expansion ports which is connected with the FPGA carrier board by two 100 pin inter board connectors The inter board connector uses AMP Tyco board to board connector 517...

Страница 20: ...FPGA Video Processing Development Platform AV6045 User Manual 20 54 Contact Email rachel zhou alinx com cn Figure 3 5 1 Expansion Ports P1...

Страница 21: ...FPGA Video Processing Development Platform AV6045 User Manual 21 54 Contact Email rachel zhou alinx com cn Figure 3 5 2 Expansion Ports P2...

Страница 22: ...d work normally the FPGA expansion baord needs to provide a 5V power supply to the core board through the expansion ports The power supply voltage of the core board ranges from 4 5V to 5 5V and the cu...

Страница 23: ...ed to the USB port of the computer When the user supplies power to the core board through the Mini USB port J2 it cannot be powered through the carrier board Otherwise current conflict may occur and t...

Страница 24: ...Contact Email rachel zhou alinx com cn and the 27MHz clock is connected to the B10 pin of the FPGA Figure 3 7 1 Crystal oscillator Schematic Figure 3 7 2 Crystal oscillator on the Core Board Crystal...

Страница 25: ...board one of which is the power indicator light PWR one is the configuration LED light DONE and four are the user LED light When the core board is powered the power indicator will illuminate when the...

Страница 26: ...nx com cn The schematic diagram of the four user LED sections is shown below In Figure 3 8 3 When the FPGA pin output is logic 0 the LED will be lit Figure 3 8 3 User LED Schemaitc Figure 3 8 4 User L...

Страница 27: ...rocessing Development Platform AV6045 User Manual 27 54 Contact Email rachel zhou alinx com cn Part 3 9 Structure Diagram Figure 3 9 1 AC6045 FPGA Core board Top view Figure 3 9 2 AC6045 FPGA Core boa...

Страница 28: ...ough the previous function introduction you can understand the function of the carrier board part 4 channel Video Input TW2867 1 channel HDMI Input SiI9013 1 channel VGA Output ADV7123 1 channel HDMI...

Страница 29: ...screen display through VGA interface 2 After 4 channels of video signals are collected by TW2867 they are displayed on 4 split screen display through HDMI interface 3 Picture in picture PIP mode via...

Страница 30: ...put by the FPGA is 24 bit color of which 8 colors are red green and blue In the schematic design the 8 bit data of the red green and blue output of the FPGA is connected to the 3 way DA of the ADV7123...

Страница 31: ...HS F18 VGA_VS J17 VGA_R7 T22 VGA_R6 R22 VGA_R5 T21 VGA_R4 R20 VGA_R3 AB7 VGA_R2 AB8 VGA_R1 Y7 VGA_R0 AA8 VGA_G7 M22 VGA_G6 L22 VGA_G5 M21 VGA_G4 L20 VGA_G3 P22 VGA_G2 N22 VGA_G1 P21 VGA_G0 N20 VGA_B7...

Страница 32: ...inx com cn of Silion Image which supports up to 1080P 60Hz output and supports 3D output Among them IIC interface of SIL9134 is connected with STM32F103 SIL9134 is initialized and controlled by STM32F...

Страница 33: ...MI Output interafce on the carrier board HDMI Output Interface Pin Assignment Pin Name FPGA Pin 9134_CLK Y12 9134_HS U22 9134_VS U20 9134_DE V22 9134_D 0 Y18 9134_D 1 U13 9134_D 2 W18 9134_D 3 U14 913...

Страница 34: ...P20 9134_D 22 N19 9134_D 23 V21 Part 4 4 HDMI Input Interface The HDMI input interface used the SIL9013 HDMI decoder chip of Silion Image which supports up to 1080P 60Hz input and Support data output...

Страница 35: ...MI Input Interface on the FPGA Board HDMI Input Interface Pin Assignment Pin Name FPGA Pin 9013_CLK AA12 9013_HS Y8 9013_VS W8 9013_DE V7 9013_D 0 W10 9013_D 1 W9 9013_D 2 Y10 9013_D 3 R8 9013_D 4 Y9...

Страница 36: ...5 9013_D 21 Y14 9013_D 22 Y16 9013_D 23 AB16 Part 4 5 Video input interface Select Techwell TW2867 input 4 composite video signals PAL NTSC SECAM automatic identification output BT656 multiplexable bu...

Страница 37: ...Video Processing Development Platform AV6045 User Manual 37 54 Contact Email rachel zhou alinx com cn Figure 4 5 1 Video Input Interface Schematic Figure 4 5 2 Video Input Interface on the carrier bo...

Страница 38: ...h the FPGA through the GMII interface RTL8211EG supports MDI MDX adaptive various speed adaptations Master Slave adaptation and support for MDIO bus for PHY register management The RTL8211EG will dete...

Страница 39: ...provided by the PHY chip the transmit clock E_GTXC is provided by the FPGA and the data is sampled on the rising edge of the clock When the network is connected to 100M Ethernet the data transmission...

Страница 40: ...lock E_TXD0 E20 Transmit Data bit0 E_TXD1 E22 Transmit Data bit1 E_TXD2 D20 Transmit Data bit2 E_TXD3 F21 Transmit Data bit3 E_TXEN H18 Transmit enable signal E_TXC G22 MII Transmit Clock E_RXC H21 RG...

Страница 41: ...ement Data Part 4 7 ARM Controller An ARM chip STM32F103 is mounted on the carrier board and each interface chip is reset through the IO port and the registers of each interface chip and the data comm...

Страница 42: ...045 User Manual 42 54 Contact Email rachel zhou alinx com cn At the same time the ARM chip also brings out real time clock EEPROM 4 LEDs and serial ports Part 4 7 1 Real Time Clock Figure 4 7 3 RTC Sc...

Страница 43: ...Contact Email rachel zhou alinx com cn ARM corresponding pin Pin Name ARM Pin RTC_SCLK 15 RTC_IO 16 RTC_RESET 14 Part 4 7 2 EEPROM Figure 4 7 5 EEPROM Schematic Figure 4 7 6 EEPROM on the carrier boar...

Страница 44: ...ment Platform AV6045 User Manual 44 54 Contact Email rachel zhou alinx com cn Part 4 7 3 LED Figure 4 7 7 LED Schematic Figure 4 7 8 LED on the carrier board ARM corresponding pin Pin Name ARM Pin LED...

Страница 45: ...ser Manual 45 54 Contact Email rachel zhou alinx com cn Part 4 7 4 USB to Serial Port Figure 4 7 9 USB to Serial Port Schematic Figure 4 7 10 USB to Serial Port on the expansion port ARM corresponding...

Страница 46: ...linx com cn Part 4 7 5 SD Card Slot ARM communicates with the Micro SD card through the SPI interface for reading and storing SD card data Figure 4 7 11 Mini SD Schematic Figure 4 7 12 SD Card Slot on...

Страница 47: ...camera interface that can be connected to the OV7670 camera module and the OV5640 camera module for video capture After acquisition the monitor can be connected via HDMI or VGA interface for display O...

Страница 48: ...4 9 Expansion Header The carrier board is reserved with one 0 1inch spacing standard 40 pin expansion header J13 which is used to connect the ALINX modules or the external circuit designed by the use...

Страница 49: ...el zhou alinx com cn circuit of the expansion port J13 is shown in Figure 3 9 1 Figure 4 9 1 Expansion header J13 schematic Figure 4 9 2 Expansion header J13 on the Carrier board J13 Expansion Header...

Страница 50: ...16 29 B16 30 A16 31 C17 32 A17 33 B18 34 A18 35 E16 36 C19 37 GND 38 GND 39 D3V3 40 D3V3 Part 4 10 JTAG Interface A JTAG interface is reserved on the FPGA carrier board for downloading FPGA programs o...

Страница 51: ...not to hot swap when JTAG cable is plugged and unplugged Part 4 11 Buttons The FPGA carrier board contains two user buttons KEY1 KEY2 All buttons are connected to the normal IO of the FPGA The button...

Страница 52: ...nt Net Name FPGA PIN KEY1 J22 KEY2 K22 Part 4 12 Power Supply The power input voltage of the FPGA development board is DC5V It is converted into D3V3 D1V2 D1V8 three way power supply through three way...

Страница 53: ...FPGA Video Processing Development Platform AV6045 User Manual 53 54 Contact Email rachel zhou alinx com cn Figure 4 12 1 Power Design Schematic on the carrier board...

Страница 54: ...FPGA Video Processing Development Platform AV6045 User Manual 54 54 Contact Email rachel zhou alinx com cn Figure 4 12 2 Power Supply circuit on the carrier board...

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