FPGA Video Processing Development Platform AV6045 User Manual
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Figure 4-6-2: Gigabit Ethernet interface on the Carrier board
Gigabit Ethernet pin assignments
:
Pin Name
FPGA Pin
Description
E_GCLK
K19
RGMII transmit clock
E_TXD0
E20
Transmit Data bit0
E_TXD1
E22
Transmit Data bit1
E_TXD2
D20
Transmit Data bit2
E_TXD3
F21
Transmit Data bit3
E_TXEN
H18
Transmit enable signal
E_TXC
G22
MII Transmit Clock
E_RXC
H21
RGMII Receive Clock
E_RXDV
K21
Receive data valid signal
E_RXD0
J20
Receive Data Bit0
E_RXD1
L19
Receive Data Bit1
E_RXD2
H22
Receive Data Bit2
E_RXD3
M20
Receive Data Bit3
E_CRS
H20
Carrier Sense Signal
E_RESET
D19
Reset Signal
E_MDC
J19
MIMO Management Clock