FusionServer G5500 V6 Server
Technical White Paper
4 Logic Structure
2023-02-14
15
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The processors interconnect with each other through three UPI links at a speed
of up to 11.2 GT/s.
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The processors connect to the PCIe riser card through the PCIe buses, and the
riser card connects to the mainboard through cables. Therefore, the processors
can be flexibly configured as required.
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CPU 1 supports one OCP 3.0 network adapter, and CPU 2 supports two OCP 3.0
network adapters.
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The PCIe RAID controller card on the mainboard connects to CPU 1 through
PCIe buses, and connects to the drive backplane through SAS signal cables. A
variety of drive backplanes are provided to support different local storage
configurations.
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The LBG-R Platform Controller Hub (PCH) is integrated on the mainboard to
support five USB 3.0 ports.
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The BMC management chip integrated on the mainboard provides a video
graphics array (VGA) port, a management network port, and a serial port.
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The G5500 V6 supports multiple logical topologies, cascaded and balanced
topologies, and can be configured using the management software to quickly
adapt to different service scenarios and achieve optimal service performance.
The details are as follows:
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As shown in Figure 4-2, the balanced topology is applicable to large-scale
deep learning training.
Figure 4-2
Balanced topology
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As shown in Figure 4-3, the cascaded topology is applicable to small- and
medium-scale deep learning training and inference, public cloud, and HPC
scenarios.
