XESS XStend, Руководство пользователя

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The design files for this example should be found in C:\XST-PROJ\EXP2. The steps for
compiling and testing the design using an XS40 combined with an XStend Board are as follows:
•
Synthesize the ABEL code in the VGACORE.ABL for an XC4005XL FPGA.
•
Compile the synthesized netlist using the EXP2_40.UCF constraint file.
•
Mount an XS40 Board in the XStend Board and attach the downloading cable from the
XS40 to the PC parallel port. Apply 9VDC though jack J9 of the XS40. Place a shunt on
jumper J11 to keep the XStend codec disabled. Attach a video monitor to the VGA
connector of the XStend Board.
•
Download the EXP2.BIT file into the XS40/XStend combination and initialize the RAM with
a pattern to display on the monitor with the command:
XSLOAD TESTPATT.HEX
EXP2.BIT
.
•
Observe the results on the video monitor.
The steps for compiling and testing the design using an XS95 combined with an XStend Board
are as follows:
•
Synthesize the ABEL code in the EXP2.ABL for an XC95108 CPLD.
•
Compile the synthesized netlist using the EXP2_95.UCF constraint file.
•
Generate an SVF file for the design.
•
Mount an XS95 Board in the XStend Board and attach the downloading cable from the
XS95 to the PC parallel port. Apply 9VDC though jack J9 of the XS95. Place a shunt on
jumper J11 to keep the XStend codec disabled. Attach a video monitor to the VGA
connector of the XStend Board.
•
Download the EXP2.SVF file into the XS95/XStend combination and initialize the RAM
with a pattern to display on the monitor with the command:
XSLOAD TESTPATT.HEX
EXP2.SVF
.
•
Observe the results on the video monitor.
Listing 16: ABEL code for testing the XStend VGA.
001- MODULE VGACORE
002- TITLE 'VGA signal generator'
003-
004- " This implementation does a 256x240 screen with 4-bit pixels
005-
006- DECLARATIONS
007- "------ external signals -------
008- rst
PIN; "uC reset control
009- push_reset_ PIN; "reset