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Production Data

WM8976

PD, Rev 4.5, November 2011

Figure 23 ALC Operation Above Noise Gate Threshold

Содержание WM8976

Страница 1: ...nd 13MHz The WM8976 operates at analogue supply voltages from 2 5V to 3 3V although the digital core can operate at voltages down to 1 71V to save power The speaker outputs and OUT3 4 line outputs can...

Страница 2: ...WIRE MODE 17 INTERNAL POWER ON RESET CIRCUIT 18 DEVICE DESCRIPTION 20 INTRODUCTION 20 INPUT SIGNAL PATH 22 ANALOGUE TO DIGITAL CONVERTER ADC 28 INPUT LIMITER AUTOMATIC LEVEL CONTROL ALC 32 OUTPUT SIGN...

Страница 3: ...Production Data WM8976 w PD Rev 4 5 November 2011 3 APPLICATION INFORMATION 111 RECOMMENDED EXTERNAL COMPONENTS 111 PACKAGE DIAGRAM 112 IMPORTANT NOTICE 113 ADDRESS 113 REVISION HISTORY 114...

Страница 4: ...NFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8976CGEFL V 25 C to 85 C 32 lead QFN 5 x 5 mm Pb free MSL3 260 o C WM8976CGEFL RV 25 C to 85 C 3...

Страница 5: ...face Data Input 2 Wire Control Interface Data Input 18 MODE Digital Input Control Interface Selection 19 AUXL Analogue input Left Auxiliary input 20 AUXR Analogue input Right Auxiliary input 21 OUT4 A...

Страница 6: ...MSL3 out of bag storage for 168 hours at 30 C 60 Relative Humidity Supplied in moisture barrier bag The Moisture Sensitivity Level for each package type is specified in Ordering Information CONDITION...

Страница 7: ...in Boost on PGA input Boost disabled 0 dB Boost enabled 20 dB Maximum Gain from AUXL or L2 input to boost mixer 6 dB Minimum Gain from AUXL or L2 input to boost mixer 12 dB Gain step size to boost mix...

Страница 8: ...ep into mixer Guaranteed monotonic 3 dB Analogue Outputs LOUT1 ROUT1 LOUT2 ROUT2 Maximum Programmable Gain 6 dB Minimum Programmable Gain 57 dB Programmable Gain step size Guaranteed monotonic 1 dB Mu...

Страница 9: ...HD N performance will be reduced 2 Note when BEEP path is not enabled then AUXL and AUXR have the same input impedances 3 Hold Time is the length of time between a signal detected being too quiet and...

Страница 10: ...DD SPKVDD DBVDD 3 3 DCVDD 1 8 Speaker Power vs THD N 8Ohm BTL Load 100 90 80 70 60 50 40 30 20 10 0 0 00 100 00 200 00 300 00 400 00 500 00 600 00 700 00 800 00 900 00 1000 00 Output Power mW THD N dB...

Страница 11: ...t will fall to nearer 15uA when thermal shutdown sensor is disabled Table 1 Power Consumption ESTIMATING SUPPLY CURRENT When either the DAC or ADC is enabled approximately 7mA will be drawn from DCVDD...

Страница 12: ...5K 0 3 less than 0 1 for 75K 300K settings ROUT1EN 0 4 LOUT1EN 0 4 BOOSTENL 0 2 INPPGAENL 0 2 ADCENL 2 6 x64 ADCOSR 0 4 9 x128 ADCOSR 1 OUT4EN 0 2 OUT3EN 0 2 LOUT2EN 1mA from SPKVDD 0 2mA from AVDD i...

Страница 13: ...Production Data WM8976 w PD Rev 4 5 November 2011 13 AUDIO PATHS OVERVIEW Figure 1 WM8976 Audio Signal Paths...

Страница 14: ...ND 0V TA 25 o C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK cycle time TMCLKY MCLK SYSCLK 256fs 81 38 ns MCLK input to PLL Note 1 20 ns MCLK duty cycle TMCLKDS 60...

Страница 15: ...CE TIMING SLAVE MODE Figure 4 Digital Audio Data Timing Slave Mode Test Conditions DCVDD 1 8V DBVDD AVDD SPKVDD 3 3V DGND AGND SPKGND 0V TA 25 o C Slave Mode fs 48kHz MCLK 256fs 24 bit data unless oth...

Страница 16: ...ata unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 80 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low t...

Страница 17: ...8kHz MCLK 256fs 24 bit data unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 0 526 kHz SCLK Low Pulse Width t1 1 3 us SCLK High Pulse Width t...

Страница 18: ...Sequence where AVDD is Powered before DVDD Figure 8 shows a typical power up sequence where AVDD comes up first When AVDD goes above the minimum threshold Vpora there is enough voltage for the circui...

Страница 19: ...PORB is asserted low whenever DVDD drops below the minimum threshold Vpord_off SYMBOL MIN TYP MAX UNIT Vpora 0 4 0 6 0 8 V Vpora_on 0 9 1 2 1 6 V Vpora_off 0 4 0 6 0 8 V Vpord_on 0 5 0 7 0 9 V Vpord_...

Страница 20: ...conjunction with a mixed analogue digital automatic level control ALC which keeps the recording volume constant LINE INPUTS AUXL AUXR The inputs AUXL and AUXR can be used as a stereo line input or as...

Страница 21: ...E pin In 2 wire mode the address of the device is fixed as 0011010 CLOCKING SCHEMES WM8976 offers the normal audio DAC clocking scheme operation where 256fs MCLK is provided to the DAC and ADC A PLL i...

Страница 22: ...y of ways to accommodate single ended or differential microphones There is an auxiliary input pin which can be fed into to the input boost mix stage as well as driving into the output path A bypass pa...

Страница 23: ...amplifier to the PGA output is always common and controlled by the register bits INPPGAVOLL 5 0 These register bits also affect the LIP pin when LIP2INPPGA 1 the L2 pin when L2_2INPPGA 1 and the L2 pi...

Страница 24: ...ime as shown in Figure 11 Figure 11 Simultaneous Left and Right Volume Updates If the volume is adjusted while the signal is a non zero value an audible click can occur as shown in Figure 12 Figure 12...

Страница 25: ...ion If there is a long period where no zero crossing occurs a timeout circuit in the WM8980 will automatically update the volume The volume updates will occur between one and two timeout periods depen...

Страница 26: ...output and the L2 input pin can be used as a line input bypassing the input PGA These three inputs can be mixed together and have individual gain boost adjust as shown in Figure 15 Figure 15 Input Bo...

Страница 27: ...IASING CIRCUIT The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network Refer to the Applications I...

Страница 28: ...and cause distortion ADC DIGITAL FILTERS The ADC filters perform true 24 bit signal processing to convert the raw multi bit oversampled data from the ADC to the correct sampling frequency to be outpu...

Страница 29: ...ut off frequency selectable via the HPFCUT register The cut off frequencies when HPFAPP 1 are shown in Table 15 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R14 ADC Control 8 HPFEN 1 High Pass Filte...

Страница 30: ...ally only update when one of the NFU bits is set high R28 Notch Filter 2 6 0 NFA0 6 0 0 Notch filter a0 coefficient bits 6 0 8 NFU 0 Notch filter update The notch filter values used internally only up...

Страница 31: ...nearest whole number These values are then converted to a 2 s complement notation NfnA0 12 0 13 h1F95 Converting to 2 s complement NFA0 14 h4000 14 h1F95 14 h206B NfnA1 12 0 13 h1F85 Converting to 2 s...

Страница 32: ...he ALCMODE register normal mode and peak limiter mode The ALC limiter function is enabled by setting the register bit R32 8 ALCSEL REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R32 20h ALC Control 1...

Страница 33: ...0000 410us 3 28ms 23 6ms 0001 820us 6 56ms 47 2ms 0010 1 64ms 13 1ms 94 5ms time doubles with every step 1010 or higher 420ms 3 36s 24 2s 0011 5 8ms 6dB Decay gain ramp up time ALCMODE 1 Per step Per...

Страница 34: ...Control Registers WHEN THE ALC IS DISABLED THE INPUT PGA REMAINS AT THE LAST CONTROLLED VALUE OF THE ALC AN INPUT GAIN UPDATE MUST BE MADE BY WRITING TO THE INPPGAVOLL R REGISTER BITS NORMAL MODE In...

Страница 35: ...ows an example of limiter mode Figure 19 ALC Limiter Mode Operation ALC LIMITER MODE INITIALISATION SEQUENCE In order to properly initialise the ALC function the following sequence of register writes...

Страница 36: ...pecified by the SR register NORMAL MODE ALCMODE 0 Normal Mode ALCATK tATK tATK6dB tATK90 0000 104 s 832 s 6ms 0001 208 s 1 66ms 12ms 0010 416 s 3 33ms 24ms 0011 832 s 6 66ms 48ms 0100 1 66ms 13 3ms 96...

Страница 37: ...0111 2 9ms 23 2ms 167ms 1000 5 81ms 46 5ms 335ms 1001 11 6ms 93ms 669ms 1010 23 2ms 186ms 1 34s Attack Time s ALCMODE 1 Limiter Mode ALCDCY tDCYLIM tDCYLIM6dB tDCYLIM90 0000 90 8 s 726 s 5 23ms 0001 1...

Страница 38: ...GA 2 0 ALCMIN 000 Set minimum gain of PGA Table 21 ALC Max Min Gain In normal mode ALCMAX sets the maximum boost which can be applied to the signal In limiter mode ALCMAX will normally have no effect...

Страница 39: ...en the ALCMAX and ALCMIN limits ALC HOLD TIME NORMAL MODE ONLY In Normal mode the ALC has an adjustable hold time which sets a time delay before the ALC begins its decay phase gain increasing The hold...

Страница 40: ...WM8976 Production Data w PD Rev 4 5 November 2011 40 Figure 21 ALCLVL...

Страница 41: ...w PD Rev 4 5 November 2011 41 Figure 22 ALC Hold Time ALCHLD tHOLD s 0000 0 0001 2 67ms 0010 5 34ms 0011 10 7ms 0100 21 4ms 0101 42 7ms 0110 85 4ms 0111 171ms 1000 342ms 1001 684ms 1010 1 37s Table 2...

Страница 42: ...against a noise gate threshold NGTH The noise gate cuts in when Signal level at ADC dBFS NGTH dBFS PGA gain dB Mic Boost gain dB This is equivalent to Signal level at input pin dBFS NGTH dBFS The PGA...

Страница 43: ...Production Data WM8976 w PD Rev 4 5 November 2011 43 Figure 23 ALC Operation Above Noise Gate Threshold...

Страница 44: ...The mixers and output drivers can be separately enabled by individual control bits see Analogue Outputs Thus it is possible to utilise the analogue mixing and amplification provided by the WM8976 irr...

Страница 45: ...n enabled gradually attenuates the volume of the digital signal to zero When disabled the gain will ramp back up to the digital gain setting This function is enabled by default To play back an audio s...

Страница 46: ...reg 11 or 12 R12 Right DAC Digital Volume 7 0 DACVOLR 7 0 11111111 0dB Right DAC Digital Volume Control 0000 0000 Digital Mute 0000 0001 127dB 0000 0010 126 5dB 0 5dB steps up to 1111 1111 0dB 8 DACV...

Страница 47: ...shold the signal is amplified at a specific decay rate controlled by LIMDCY register bits until a gain of 0dB is reached Both threshold levels are controlled by the LIMLVL register bits The upper thre...

Страница 48: ...ms 1010 96ms 1011 to 1111 192ms 7 4 LIMDCY 0011 Limiter Decay time per 6dB gain change for 44 1kHz sampling Note that these will scale proportionally with sample rate 0000 750us 0001 1 5ms 0010 3ms 00...

Страница 49: ...Table 31 EQ and 3D Enhancement DAC or ADC Path Select The equaliser consists of low and high frequency shelving filters Band 1 and 5 and three peak filters for the centre bands Each has adjustable cut...

Страница 50: ...4 0 EQ4G 01100 0dB Band 4 Gain Control See Table 37 for details 6 5 EQ4C 01 Band 4 Centre Frequency 00 1 8kHz 01 2 4kHz 10 3 2kHz 11 4 1kHz 8 EQ4BW 0 Band 4 Bandwidth Control 0 narrow bandwidth 1 wid...

Страница 51: ...ured as a stereo line out OUT3 is left output and OUT4 is right output OUT4 can also be used to provide a mono mix of left and right channels LOUT2 ROUT2 OUT3 and OUT4 are supplied from SPKVDD and are...

Страница 52: ...WM8976 Production Data w PD Rev 4 5 November 2011 52 Figure 27 Left Right Output Channel Mixers...

Страница 53: ...t mixer control 0 DACL2LMIX 1 Left DAC output to left output mixer 0 not selected 1 selected 1 BYPL2LMIX 0 Bypass path from the input boost output to left output mixer 0 not selected 1 selected 4 2 BY...

Страница 54: ...000 Aux right channel input to right mixer volume control 000 15dB 001 12dB 101 0dB 110 3dB 111 6dB R3 Power management 3 2 LMIXEN 0 Left output channel mixer enable 0 disabled 1 enabled 3 RMIXEN 0 R...

Страница 55: ...cross only 0 Change gain immediately 6 ROUT1MUTE 0 Right headphone output mute 0 Normal operation 1 Mute 5 0 ROUT1VOL 111001 Right headphone output volume 000000 57dB 111001 0dB 111111 6dB 8 HPVU Not...

Страница 56: ...outputs only to headphones and not to the line input of another device Although the built in short circuit protection will prevent any damage to the headphone outputs such a connection may be noisy a...

Страница 57: ...ts and can be any combination of the DAC output the Bypass path output of the input boost stage and the AUX input The LOUT2 ROUT2 volume is controlled by the LOUT2VOL ROUT2VOL register bits Gains over...

Страница 58: ...RPGA2INV 0 Mute input to INVROUT2 mixer 4 INVROUT2 0 Invert ROUT2 output 3 1 BEEPVOL 000 AUXR input to ROUT2 inverter gain 000 15dB 111 6dB 0 BEEPEN 0 0 mute AUXR beep input 1 enable AUXR beep input T...

Страница 59: ...e mixer for OUT3 and one for OUT4 as shown in Figure 31 The OUT3 and OUT4 output stages are powered from SPKVDD and SPKGND The individually controllable outputs also incorporate an optional 1 5x boost...

Страница 60: ...ted by 6dB 4 LMIX2OUT4 0 Left DAC mixer to OUT4 0 disabled 1 enabled 3 LDAC2OUT4 0 Left DAC to OUT4 0 disabled 1 enabled 1 RMIX2OUT4 0 Right DAC mixer to OUT4 0 disabled 1 enabled 0 RDAC2OUT4 1 Right...

Страница 61: ...1 DC AVDD 2 1 OUT4 output gain 1 5 DC 1 5 x AVDD 2 R1 Power management 1 8 BUFDCOPEN 0 Dedicated buffer for DC level shifting output stages when in 1 5x gain boost configuration 0 Buffer disabled 1 B...

Страница 62: ...xer path For example DACL can be directly input to the OUT3 mixer giving a 180 phase shift at the OUT3 mixer output However if DACL is input to the OUT3 mixer via the left mixer an additional phase sh...

Страница 63: ...1 0 0 0 0 180 1 180 1 180 1 180 1 0 1 0 1 Stereo DAC playback to LOUT1 ROUT1 and LOUT2 ROUT2 and OUT4 OUT3 Speaker boost enabled 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 5 0 1 5 Stereo DAC playback to LOUT1 R...

Страница 64: ...1 ON 0 OFF Table 50 Output Stages Power Management Control THERMAL SHUTDOWN The speaker outputs can drive very large currents To protect the WM8976 from overheating a thermal shutdown circuit is inclu...

Страница 65: ...utput of the DC level shift buffer at 1 5xAVDD 2 when disabled Figure 34 summarises the tie off options for the speaker and mono output pins Figure 34 Unused Input Output Pin Tie off Buffers L ROUT2EN...

Страница 66: ...section for timing information MASTER AND SLAVE MODE OPERATION The WM8976 audio interface may be configured as either master or slave As a master interface device the WM8976 generates BCLK and LRC an...

Страница 67: ...unused BCLK cycles after each LRC transition Figure 36 Right Justified Audio Interface assuming n bit word length In I 2 S mode the MSB is available on the second rising edge of BCLK following a LRC...

Страница 68: ...K selectable by LRP following a rising edge of LRC Right channel data immediately follows left channel data Depending on word length BCLK frequency and sample rate there may be unused BCLK cycles betw...

Страница 69: ...e mode A B select 1 MSB is available on 1st BCLK rising edge after LRC rising edge mode B 0 MSB is available on 2nd BCLK rising edge after LRC rising edge mode A 8 BCP BCLK polarity 0 normal 1 inverte...

Страница 70: ...output under control of CLKSEL 000 divide by 1 001 divide by 1 5 010 divide by 2 011 divide by 3 100 divide by 4 101 divide by 6 110 divide by 8 111 divide by 12 8 CLKSEL 1 Controls the source of the...

Страница 71: ...0 48kHz 001 32kHz 010 24kHz 011 16kHz 100 12kHz 101 8kHz 110 111 reserved Table 56 Sample Rate Control MASTER CLOCK AND PHASE LOCKED LOOP PLL The WM8976 has an on chip phase locked loop PLL circuit th...

Страница 72: ...ould be chosen to ensure 5 PLLN 13 There is a fixed divide by 4 in the PLL and a selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement Enabling the divide by...

Страница 73: ...98 304 2 2 9 990243 9 FD809F 19 8 11 29 90 3168 2 2 9 122909 9 1F76F7 19 8 12 288 98 304 2 2 9 929697 9 EE009E 24 11 29 90 3168 2 2 7 5264 7 86C226 24 12 288 98 304 2 2 8 192 8 3126E8 26 11 29 90 316...

Страница 74: ...mended by the G 711 standard all 8 bits are inverted for law all even data bits are inverted for A law The data will be transmitted as the first 8 MSB s of data Companding converts 13 bits law or 12 b...

Страница 75: ...2 A Law Companding GENERAL PURPOSE INPUT OUTPUT The WM8976 has two dual purpose input output pins CSB GPIO1 CSB GPIO pin L2 GPIO2 Line input headphone detection input The GPIO2 function is provided fo...

Страница 76: ...enables from toggling multiple times due to input glitches This de bounce circuit is clocked from a slow clock with period 2 21 x MCLK and is enabled by the SLOWCLKEN bit Notes 1 The SLOWCLKEN bit mu...

Страница 77: ...0000 Output enables when selected jack detection input is logic 0 0 OUT1_EN_0 1 OUT2_EN_0 2 OUT3_EN_0 3 OUT4_EN_0 7 4 JD_EN1 0000 Output enables when selected jack detection input is logic 1 0000 0011...

Страница 78: ...g a write once the WM8976 has acknowledged a correct address the controller sends the first byte of control data B15 to B8 i e the WM8976 register address plus the first bit of register data The WM897...

Страница 79: ...ut and decoupling capacitors to curb harmonic distortion With a larger SPKVDD louder headphone and speaker outputs can be achieved with lower distortion If SPKVDD is lower than AVDD the output signal...

Страница 80: ...rs Power up when using the output 1 5x boost stage 1 Turn on external power supplies Wait for supply voltage to settle 2 Mute all analogue outputs 3 Enable unused output chosen from L ROUT2 OUT3 or OU...

Страница 81: ...5 boost mode will cause the VMID voltage to drop to AVDD 2 midrail level and cause an output pop In addition to the power on sequence it is recommended that the zero cross functions are used when cha...

Страница 82: ...is enabled there will be LSB data bit activity on the ADCDAT pin due to system noise but no significant digital output will be present 4 The VMIDSEL and BIASEN bits must be set to enable analogue inpu...

Страница 83: ...op noise on the analogue outputs The same is also true if the DACDAT is removed at a non zero value and no mute function has been applied to the signal beforehand 3 The lineout discharge time tline_mi...

Страница 84: ...te select 0 64x lowest power 1 128x best SNR Table 67 ADC and DAC Oversampling Rate Selection VMID The analogue circuitry will not work when VMID is disabled VMIDSEL 1 0 00b The impedance of the VMID...

Страница 85: ...Jack Detect Control JD_EN1 JD_EN0 000 14 0E ADC Control HPFEN HPFAPP HPFCUT ADCOSR 128 0 0 ADCLPOL 100 15 0F ADC Digital Vol ADCVU ADCVOLL 0FF 18 12 EQ1 low shelf EQ3DMODE 0 EQ1C EQ1G 12C 19 13 EQ2 pe...

Страница 86: ...LMIX DACL2LMIX 001 51 33 Right mixer ctrl AUXRMIXVOL AUXR2RMI X 0 0 DACR2RMIX 001 52 34 LOUT1 HP volume ctrl HPVU LOUT1ZC LOUT1 MUTE LOUT1VOL 039 53 35 ROUT1 HP volume ctrl HPVU ROUT1ZC ROUT1 MUTE ROU...

Страница 87: ...anagement 5 PLLEN 0 PLL enable 0 PLL off 1 PLL on Master Clock and Phase Locked Loop PLL 4 MICBEN 0 Microphone Bias Enable 0 OFF high impedance output 1 ON Input Signal Path 3 BIASEN 0 Analogue amplif...

Страница 88: ...sabled 1 enabled Analogue Outputs 1 DACENR 0 Right channel DAC enable 0 DAC disabled 1 DAC enabled Analogue Outputs 0 DACENL 0 Left channel DAC enable 0 DAC disabled 1 DAC enabled Analogue Outputs 4 0...

Страница 89: ...es 5 05h 8 6 000 Reserved 5 WL8 0 Companding Control 8 bit mode 0 off 1 device operates in 8 bit mode Digital Audio Interfaces 4 3 DAC_COMP 00 DAC companding 00 off linear mode 01 reserved 10 law 11 A...

Страница 90: ...internal digital filters 000 48kHz 001 32kHz 010 24kHz 011 16kHz 100 12kHz 101 8kHz 110 111 reserved Audio Sample Rates 0 SLOWCLKEN 0 Slow clock enable Used for both the jack insert detect debounce ci...

Страница 91: ...put polarity 0 non inverted 1 inverted 180 degrees phase shift Output Signal Path 0 DACPOLL 0 Left DAC output polarity 0 non inverted 1 inverted 180 degrees phase shift Output Signal Path 11 0Bh 8 DAC...

Страница 92: ...off frequency See Table 15 for details Analogue to Digital Converter ADC 3 ADCOSR 128 0 ADC oversample rate select 0 64x lowest power 1 128x best SNR Power Management 2 1 00 Reserved 0 ADCLPOL 0 ADC p...

Страница 93: ...tre Frequency 00 650Hz 01 850Hz 10 1 1kHz 11 1 4kHz Output Signal Path 4 0 EQ3G 01100 EQ Band 3 Gain Control See Table 37 for details Output Signal Path 21 15h 8 EQ4BW 0 EQ Band 4 Bandwidth Control 0...

Страница 94: ...0001 188s 0010 375us 0011 750us 0100 1 5ms 0101 3ms 0110 6ms 0111 12ms 1000 24ms 1001 48ms 1010 96ms 1011 to 1111 192ms Output Signal Path 25 19h 8 7 00 Reserved 6 4 LIMLVL 000 Programmable signal thr...

Страница 95: ...The notch filter values used internally only update when one of the NFU bits is set high Analogue to Digital Converter ADC 7 0 Reserved 6 0 NFA1 13 7 0000000 Notch Filter a1 coefficient bits 13 7 Anal...

Страница 96: ...put Limiter Automatic Level Control ALC 34 22h 8 ALCMODE 0 Determines the ALC mode of operation 0 ALC mode 1 Limiter mode Input Limiter Automatic Level Control ALC 7 4 ALCDCY 3 0 0011 Decay gain ramp...

Страница 97: ...y 2 before input to PLL Master Clock and Phase Locked Loop PLL 3 0 PLLN 3 0 1000 Integer N part of PLL input output frequency ratio Use values greater than 5 and less than 13 Master Clock and Phase Lo...

Страница 98: ...terminal Input Signal Path 0 LIP2INP PGA 1 Connect LIP pin to input PGA amplifier positive terminal 0 LIP not connected to input PGA 1 input PGA amplifier positive terminal connected to LIP constant i...

Страница 99: ...cted 1 selected Analogue Outputs 5 DACR2LMIX 0 Right DAC output to left output mixer 0 not selected 1 selected Analogue Outputs 4 OUT4 BOOST 0 0 OUT4 output gain 1 DC AVDD 2 1 OUT4 output gain 1 5 DC...

Страница 100: ...Analogue Outputs 4 1 0000 Reserved 0 DACR2R MIX 1 Right DAC output to right output mixer 0 not selected 1 selected Analogue Outputs 52 34h 8 HPVU N A LOUT1 and ROUT1 volumes do not update until a 1 i...

Страница 101: ...ot update until a 1 is written to SPKVU in reg 54 or 55 Analogue Outputs 7 ROUT2ZC 0 Speaker volume zero cross enable 1 Change gain on zero cross only 0 Change gain immediately Analogue Outputs 6 ROUT...

Страница 102: ...er in this mode Analogue Outputs 5 HALFSIG 0 0 OUT4 normal output 1 OUT4 attenuated by 6dB Analogue Outputs 4 LMIX2OUT4 0 Left DAC mixer to OUT4 0 disabled 1 enabled Analogue Outputs 3 LDAC2OUT4 0 Lef...

Страница 103: ...ADC High Pass Filter High Pass Filter Corner Frequency 3dB 3 7 Hz 0 5dB 10 4 0 1dB 21 6 DAC Filter Passband 0 035dB 0 0 454fs 6dB 0 5fs Passband Ripple 0 035 dB Stopband 0 546fs Stopband Attenuation...

Страница 104: ...e 128xOSR 160 140 120 100 80 60 40 20 0 20 0 0 5 1 1 5 2 2 5 Frequency fs Response dB 2 6 2 65 2 7 2 75 2 8 2 85 2 9 2 95 3 3 05 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 0 5 Frequency fs Response dB...

Страница 105: ...0 5 0 5 10 15 20 25 30 35 40 45 Frequency Hz Response dB Figure 53 ADC Highpass Filter Response HPFAPP 0 60 50 40 30 20 10 0 10 0 200 400 600 800 1000 1200 Frequency Hz Response dB 80 70 60 50 40 30 2...

Страница 106: ...her the ADC path or the DAC path The plots from Figure 57 to Figure 70 show the frequency responses of each filter with a sampling frequency of 48kHz firstly showing the different cut off centre frequ...

Страница 107: ...fs Figure 58 EQ Band 1 Gains for Lowest Cut off Frequency 10 1 10 0 10 1 10 2 10 3 10 4 10 5 15 10 5 0 5 10 15 Frequency Hz Magnitude dB 10 1 10 0 10 1 10 2 10 3 10 4 10 5 15 10 5 0 5 10 15 Frequency...

Страница 108: ...dB 10 1 10 0 10 1 10 2 10 3 10 4 10 5 15 10 5 0 5 10 15 Frequency Hz Magnitude dB Figure 62 EQ Band 3 Peak Filter Centre Frequencies EQ3B Figure 63 EQ Band 3 Peak Filter Gains for Lowest Cut off Freq...

Страница 109: ...Q3B Figure 66 EQ Band 4 Peak Filter Gains for Lowest Cut off Frequency EQ4BW 0 10 2 10 1 10 0 10 1 10 2 10 3 10 4 15 10 5 0 5 10 15 Frequency Hz Magnitude dB Figure 67 EQ Band 4 EQ3BW 0 EQ3BW 1 10 1 1...

Страница 110: ...neously The blue traces show each band lowest cut off centre frequency with 12dB gain The red traces show the cumulative effect of all bands with 12dB gain and all bands 12dB gain with EqxBW 0 for the...

Страница 111: ...Production Data WM8976 w PD Rev 4 5 November 2011 111 APPLICATION INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 71 Recommended External Component Diagram...

Страница 112: ...SHALL CONFORM TO JEDEC 95 1 SPP 002 5 COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS 6 REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS A...

Страница 113: ...ms where malfunction can reasonably be expected to result in personal injury death or severe property or environmental damage Any use of products by the customer for such purposes is at the customer s...

Страница 114: ...4 REVISION HISTORY DATE REV ORIGINATOR CHANGES 29 09 11 4 5 JMacD Order codes changed from WM8976GEFL V and WM8976GEFL RV to WM8976CGEFL V and WM8976CGEFL RV to reflect change to copper wire bonding 2...

Страница 115: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Cirrus Logic WM8976 6160 FL32 M WM8976 6160 FL32 M S WM8976CGEFL V WM8976CGEFL RV...

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