WM8976
Production
Data
w
PD, Rev 4.5, November 2011
14
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 2 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T
A
= +25
o
C
PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK cycle time
T
MCLKY
MCLK=SYSCLK (=256fs)
81.38
ns
MCLK input to PLL
Note 1
20
ns
MCLK duty cycle
T
MCLKDS
60:40 40:60
Note 1:
PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
AUDIO INTERFACE TIMING – MASTER MODE
Figure 3 Digital Audio Data Timing – Master Mode (see Control Interface)
Содержание WM8976
Страница 13: ...Production Data WM8976 w PD Rev 4 5 November 2011 13 AUDIO PATHS OVERVIEW Figure 1 WM8976 Audio Signal Paths...
Страница 40: ...WM8976 Production Data w PD Rev 4 5 November 2011 40 Figure 21 ALCLVL...
Страница 43: ...Production Data WM8976 w PD Rev 4 5 November 2011 43 Figure 23 ALC Operation Above Noise Gate Threshold...
Страница 52: ...WM8976 Production Data w PD Rev 4 5 November 2011 52 Figure 27 Left Right Output Channel Mixers...
