5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
3D3V_48MPW R_S0
GEN_XTAL_IN
GEN_XTAL_OUT
3D3V_48MPW R_S0
REF2
REF0
REF1
PD#
CLKREQ0#
CLKREQ2#
CLKREQ4#
VDD_REF
CLK_SRC0T_LPRS
CLK_SRC0C_LPRS
PD#
REF0
REF2
REF1
REF0
CLK_48
RUNPW ROK_D
REF1
W LAN_CLKREQ#
CLK_SMBCLK
CLK_SMBDAT
3D3V_S0
3D3V_CLK_VDD
3D3V_S0
3D3V_CLK_VDD
3D3V_S0
3D3V_S0
1D1V_CLK_VDDIO
3D3V_CLK_VDD
1D1V_CLK_VDDIO
3D3V_S0
3D3V_S5
CLK48_USB 12
SMBD0_SB 12,16,17
CPU_CLK
6
CPU_CLK#
6
CLK_NBHT_CLK
9
CLK_NBHT_CLK#
9
CLK_PCIE_SB#
11
CLK_PCIE_SB
11
CLK_PCIE_MINI1
33
CLK_PCIE_MINI1#
33
CLK_NB_GPPSB#
9
CLK_NB_GPPSB
9
CLK_PCIE_LAN#
26
CLK_PCIE_LAN
26
CLK_NB_14M 9
CLK48_5158E 32
RUNPW ROK_D
41
CLK_NB_GFX 9
CLK_NB_GFX# 9
CLK_PCIE_PEG
52
CLK_PCIE_PEG#
52
SMBC0_SB 12,16,17
CLK_27M_M92
53
CLK_27M_SSIN
53
CLK_SB_14M 11
LAN_CLKREQ# 26
W LAN_CLKREQ# 33
Title
Size
Document Number
Rev
Date:
Sheet
of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
JV71-TR
SB
CLKGEN_ICS9LPRS480
A3
3
61
Monday, July 06, 2009
UMA
Title
Size
Document Number
Rev
Date:
Sheet
of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
JV71-TR
SB
CLKGEN_ICS9LPRS480
A3
3
61
Monday, July 06, 2009
UMA
Title
Size
Document Number
Rev
Date:
Sheet
of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
JV71-TR
SB
CLKGEN_ICS9LPRS480
A3
3
61
Monday, July 06, 2009
UMA
3000mA.80ohm
CPU_CLK(200MHz)
CL=20pF±0.2pF
Due to PLL issue on current clock chip, the SBlink clock
need to come from SRC clocks for RS740 and RS780.
Future clock chip revision will fix this.
Clock chip has internal serial terminations
for differencial pairs, external resistors are
reserved for debug purpose.
100M DIFF
GPPSB_REFCLK
100M DIFF
100M DIFF
100M DIFF(IN/OUT)*
HT_REFCLKP
RS740
RX780
RS780
NB CLOCK INPUT TABLE
NC or 100M DIFF OUTPUT
* RS780 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.
66M SE(SINGLE END)
NC
100M DIFF
100M DIFF
100M DIFF
100M DIFF
14M SE (3.3V)
14M SE (1.8V)
14M SE (1.1V)
NB CLOCKS
NC
NC
vref
HT_REFCLKN
100M DIFF
REFCLK_P
100M DIFF
REFCLK_N
NC
GFX_REFCLK
GPP_REFCLK
100M DIFF
CLKREQ# Internal
pull Low
1.1V 158R/90.9R
RS780M
OSC_14M_NB
66MHz 3.3V single ended HTT clock
SEL_SATA
REF1
SEL_HTT66
REF0
100MHz differential spreading SRC clock
1
*
0
1
0 *
100MHz differential HTT clock
100MHz non-spreading differential SATA clock
SEL_27
REF2
0
100MHz differential spreading SRC clock
27MHz non-spreading singled clock on pin 5
and 27MHz spread clock on pin 6
*
1
NB HT
NB A-Link
MINI1
LAN
SB A-Link
For SB710
for TR
2009/04/21 Pad to R By John
TP157 TPAD14-GP
TP157 TPAD14-GP
1
2
R225
10KR2J-3-GP
DY
R225
10KR2J-3-GP
DY
1
2
R229
33R2F-3-GP
R229
33R2F-3-GP
TP153 TPAD14-GP
TP153 TPAD14-GP
1
2
R224
10KR2J-3-GP
DY
R224
10KR2J-3-GP
DY
1
2
R234
75R2F-2-GP
DY
R234
75R2F-2-GP
DY
1
2
3
4
5
6
7
8
RN70
SRN10KJ-6-GP
RN70
SRN10KJ-6-GP
1
2
C495
SCD1U10V2KX-4GP
C495
SCD1U10V2KX-4GP
1
2
C476
SCD1U10V2KX-4GP
DY
C476
SCD1U10V2KX-4GP
DY
1
2
C505
SC1U10V2KX-1GP
C505
SC1U10V2KX-1GP
1
2
R231
10KR2J-3-GP
DY
R231
10KR2J-3-GP
DY
1
2
C504
SCD1U10V2KX-4GP
C504
SCD1U10V2KX-4GP
1
2
C464
SCD1U10V2KX-4GP
C464
SCD1U10V2KX-4GP
1
2
R223
10KR2J-3-GP
DY
R223
10KR2J-3-GP
DY
1
2
EC50
SC22P50V2JN-4GP
DY
EC50
SC22P50V2JN-4GP
DY
1
2
C502
SCD1U10V2KX-4GP
DY
C502
SCD1U10V2KX-4GP
DY
1
2
C509
SC33P50V2JN-3GP
C509
SC33P50V2JN-3GP
GND48
1
SMBCLK
2
SMBDAT
3
VDD
4
SRC7C_LPRS/27MHZ_NS
5
SRC7T_LPRS/27MHZ_SS
6
GND
7
SRC4C_LPRS
8
SRC4T_LPRS
9
GNDSRC
10
VDDSRC_IO
11
SRC3C_LPRS
12
SRC3T_LPRS
13
SRC2C_LPRS
14
SRC2T_LPRS
15
VDDSRC
16
VDDSRC_IO
17
GNDSRC
18
SRC1C_LPRS
19
SRC1T_LPRS
20
SRC0C_LPRS
21
SRC0T_LPRS
22
CLKREQ0#
23
GNDATIG
24
VDDATIG_IO
25
VDDATIG
26
ATIG1C_LPRS
27
ATIG1T_LPRS
28
ATIG0C_LPRS
29
ATIG0T_LPRS
30
SB_SRC1C_LPRS
31
SB_SRC1T_LPRS
32
GNDSB_SRC
33
VDDSB_SRC_IO
34
VDDSB_SRC
35
SB_SRC0C_LPRS
36
SB_SRC0T_LPRS
37
CLKREQ4#
38
CLKREQ3#
39
VDDSATA
40
SRC6C/SATAC_LPRS
41
SRC6T/SATAT_LPRS
42
GNDSATA
43
CLKREQ2#
44
CLKREQ1#
45
GNDCPU
46
VDDCPU_IO
47
VDDCPU
48
CPUKG0C_LPRS
49
CPUKG0T_LPRS
50
PD#
51
GNDHTT
52
HTT0C_LPRS/66M
53
HTT0T_LPRS/66M
54
VDDHTT
55
VDDREF
56
REF2/SEL_27
57
REF1/SEL_SATA
58
REF0/SEL_HTT66
59
GNDREF
60
X1
61
X2
62
VDD48
63
48MHZ_0
64
GND
65
U20
ICS9LPRS480BKLFT-GP
71.09480.A03
2ND = 71.00880.A03
U20
ICS9LPRS480BKLFT-GP
71.09480.A03
2ND = 71.00880.A03
1
2
C460
SC10U6D3V3MX-GP
C460
SC10U6D3V3MX-GP
1
2
R228
10KR2J-3-GP
DY
R228
10KR2J-3-GP
DY
1
2
X5
XTAL-14D31818MHZ-5-GP
2ND = 82.30005.951
82.30005.B11
X5
XTAL-14D31818MHZ-5-GP
2ND = 82.30005.951
82.30005.B11
1
2
R197
0R0603-PAD
R197
0R0603-PAD
1
2
R230
10KR2J-3-GP
DY
R230
10KR2J-3-GP
DY
1
2
R238
0R0603-PAD
R238
0R0603-PAD
1
2
C511
SC4D7U6D3V3KX-GP
DY
C511
SC4D7U6D3V3KX-GP
DY
1
2
EC49
SC22P50V2JN-4GP
DY
EC49
SC22P50V2JN-4GP
DY
1
2 R353
1KR2F-3-GP
DY
R353
1KR2F-3-GP
DY
1
2
C462
SCD1U10V2KX-4GP
C462
SCD1U10V2KX-4GP
TP159 TPAD14-GP
TP159 TPAD14-GP
1
2
R213
0R0402-PAD
R213
0R0402-PAD
1
2
C453
SCD1U10V2KX-4GP
C453
SCD1U10V2KX-4GP
1
2
C492
SCD1U10V2KX-4GP
C492
SCD1U10V2KX-4GP
1
2
C461
SCD1U10V2KX-4GP
C461
SCD1U10V2KX-4GP
1
2
R218
10MR2J-L-GP
DY
R218
10MR2J-L-GP
DY
1
2
C501
SC10U6D3V3MX-GP
C501
SC10U6D3V3MX-GP
1
2
C506
SC1U10V2KX-1GP
C506
SC1U10V2KX-1GP
1
2
C472
SCD1U10V2KX-4GP
C472
SCD1U10V2KX-4GP
1
2
R215
0R0603-PAD
R215
0R0603-PAD
1
2
3
4
RN65
SRN10J-7-GP
RN65
SRN10J-7-GP
1
2
R352
1K2R2F-1-GP
DY
R352
1K2R2F-1-GP
DY
1
2
C500
SC10U6D3V3MX-GP
C500
SC10U6D3V3MX-GP
1
2
C459 SC10U6D3V3MX-GP
C459 SC10U6D3V3MX-GP
1
2
C454
SCD1U10V2KX-4GP
C454
SCD1U10V2KX-4GP
1
2
R232
150R2F-1-GP
R232
150R2F-1-GP
1
2
C508
SC27P50V2JN-2-GP
C508
SC27P50V2JN-2-GP
1
2
R221
2R3J-GP
R221
2R3J-GP
1
2
R214
0R0402-PAD
R214
0R0402-PAD
1
2
R209
0R2J-2-GP
DY
R209
0R2J-2-GP
DY
1
2
C467
SCD1U10V2KX-4GP
C467
SCD1U10V2KX-4GP
1
2
R235
75R2F-2-GP
R235
75R2F-2-GP
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