5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
MAB7
MAB8
MAB9
MAB10
MAB0
MAB11
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
MAB12
BA0
BA2
BA1
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
RDQSB0
RDQSB1
RDQSB2
RDQSB3
RDQSB4
RDQSB5
RDQSB6
RDQSB7
W DQSB0
W DQSB1
W DQSB2
W DQSB3
W DQSB4
W DQSB5
W DQSB6
W DQSB7
ODTB1
ODTB0
CLKB0#
CLKB1
CLKB0
CLKB1#
RASB0#
RASB1#
CASB0#
CASB1#
CSB0#_0
CSB1#_0
W EB0#
W EB1#
CKEB0
CKEB1
MVREFDB
MVREFSB
TESTEN
CLKTESTA
CLKTESTB
1D5V_M92
1D5V_M92
3D3V_M92
1D5V_M92
MAB[0..12]
57,58
MDB[63..0]
57,58
BA2
57,58
BA0
57,58
BA1
57,58
DQMB#[0..7]
57,58
RDQSB[0..7]
57,58
W DQSB[0..7]
57,58
ODTB0
57
ODTB1
58
CLKB0
57
CLKB1#
58
CLKB1
58
CLKB0#
57
RASB0#
57
RASB1#
58
CASB0#
57
CASB1#
58
CSB0#_0
57
CSB1#_0
58
W EB0#
57
W EB1#
58
CKEB0
57
CKEB1
58
GPIO_VGA_22
53
GPIO_VGA_02
53
GPIO_VGA_09
53
GPIO_VGA_11
53
GPIO_VGA_00
53
GPIO_VGA_01
53
GPIO_VGA_08
53
GPIO_VGA_05
53
CRT_HSYNC
20,53
CRT_VSYNC
20,53
GPIO_VGA_13
53
GPIO_VGA_12
53
VRAM_RST
57,58
Title
Size
Document Number
Rev
Date:
Sheet
of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
JV71-TR
SA
Memory / Straps
A2
56
61
Monday, July 06, 2009
UMA
Title
Size
Document Number
Rev
Date:
Sheet
of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
JV71-TR
SA
Memory / Straps
A2
56
61
Monday, July 06, 2009
UMA
Title
Size
Document Number
Rev
Date:
Sheet
of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
JV71-TR
SA
Memory / Straps
A2
56
61
Monday, July 06, 2009
UMA
( 0.5 * VDDR1 ) ( for SSTL-1.8/SSTL-2/DDR2 )
( 0.7 * VDDR1 ) ( for GDDR3/GDDR4 )
MVREF TO GND 100R 100R 100R
MVREF TO 1.8V 100R 100R
DIVIDER RESISTORS DDR2 DDR3 GDDR3
STRAPS
PIN
DESCRIPTION
M25P05A
M25P10A
M25P20
M25P40
M25P80
Pm25LV512A
Pm25LV010A
ST
Microelectronics
Chingis
(formerly PMC)
DVPDATA(23:20)
Initialization Behavior: This signal is input during
reset (no reference clock is required). After reset,
the default state is output low (0 V).
The signals above can be left unconnected if not
used.
Tansmitter Power Savings Enable
0= 50% Tx output swing
1= Full Tx output swing
Transmitter De-emphasis Enable
0= Tx de-emphasis disabled
1= Tx de-emphasis enabled
GPIO
Size of the primary
memory apertures
128MB
256MB
64MB
32MB
512MB
1GB
2GB
4GB
GPIO[13,12,11]
x000
x001
x010
x
x
x
x
x
AMD RESERVED CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
H2SYNC, GENERICC
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
(Internal PD)
STRAPS
PIN
DESCRIPTION
TX_PWRS_ENB
TX_DEEMPH_EN
GPIO0
GPIO1
(Internal PD)
If BIOS_ROM_EN (GPIO22) = 0
(Internal PD)
If BIOS_ROM_EN (GPIO22) = 1
Manufacturer
Part Number
GPIO[13,12,11]
0100
0101
0101
0101
0101
0100
0101
BIF_GEN2_EN_A
GPIO2
0 = Advertises the PCI-E device
as 2.5GT/s
1 = Advertises the PCI-E device
as 5GT/s
GPIO[13,12,11]
GPIO5
AC_BATT
AC (Performance mode) = 3.3 V
Battery saving mode = 0.0 V
ROMSO
Serial ROM Output from ROM
GPIO8
Serial ROM Input to ROM
GPIO9
ROMSI
(Internal PD)
ROMIDCFG[3:0]
if BIOS_ROM_EN=1,then Config[3:0]
defines the ROM type
if BIOS_ROM_EN=0,then Config[3:0]
defines the primary memory apeture size
GPIO[15,20]
PWRCNTL_[1,0]
Power control signals to control the core
voltage regulator
AUD[1]
AUD[0]
VGA_VSYNC
(Internal PD)
VGA_HSYNC
AUD[1:0]
00:No audio function
01:Audio for DisplayPort and HDMI
( if adapter is detected)
10:Audio for DisplayPort only
11:Audio for both DisplayPort and HDMI
GPIO_28_TDO , GPIO21_BB_EN
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
PCIE FULL TX OUTPUT SW ING
PCIE GNE2 ENABLED
BIF_CLK_PM_EN
VGA ENABLED
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT
GPIO21
BB_EN
Back Bias (body bias) which minimizes
power consumption in battery modes.
0V = Disable
3D3V = Enable
GENERICC
CCBYPASS
1
1
1
0
0
0
X X
X
1
0
M92-M2 uses memory group B only
V
HDMI must only be enabled on systems that are
legally entitled. It is the responsibility of the system
designer to ensure that the system is entitled to
support this feature.
for TR 0408
for TR 0408
for TR 0408
40.2R PN:64.40R25.6DL
40.2R
1
2
R356
4K
7R
2F
-G
P
DIS
R356
4K
7R
2F
-G
P
DIS
1
2
R61
10KR2J-3-GP
DIS
R61
10KR2J-3-GP
DIS
1
2
R357
4K
7R
2F
-G
P
DIS
R357
4K
7R
2F
-G
P
DIS
1
2
C789
S
C
D
0
1U
50V
2K
X
-1G
P
DIS
C789
S
C
D
0
1U
50V
2K
X
-1G
P
DIS
1
2
R417
1KR2F-3-GP
DIS
R417
1KR2F-3-GP
DIS
1
2
R62
10KR2J-3-GP
DIS
R62
10KR2J-3-GP
DIS
1
2
C793
S
CD1
U1
6
V
2
K
X
-3
G
P
DIS
C793
S
CD1
U1
6
V
2
K
X
-3
G
P
DIS
1
2
C961
SC2200P50V2KX-2GP
DIS
C961
SC2200P50V2KX-2GP
DIS
1
2
R54
10KR2J-3-GP
DY
R54
10KR2J-3-GP
DY
1
2
R58
10KR2J-3-GP
DIS
R58
10KR2J-3-GP
DIS
1
2
R57
10KR2J-3-GP
DIS
R57
10KR2J-3-GP
DIS
1
2
R377
10KR2J-3-GP
DIS
R377
10KR2J-3-GP
DIS
1
2
R436
100R2F-L1-GP-U
DIS
R436
100R2F-L1-GP-U
DIS
1
2
R60
10KR2J-3-GP
DY
R60
10KR2J-3-GP
DY
1
2
R55
10KR2J-3-GP
DY
R55
10KR2J-3-GP
DY
1
2
R433
100R
2F
-L1-
G
P
-U
DIS
R433
100R
2F
-L1-
G
P
-U
DIS
1
2
R1203
4K7R2F-GP
DIS
R1203
4K7R2F-GP
DIS
1
2
R435
100R2F-L1-GP-U
DIS
R435
100R2F-L1-GP-U
DIS
1
2
C792
S
CD1
U1
6
V
2
K
X
-3
G
P
DIS
C792
S
CD1
U1
6
V
2
K
X
-3
G
P
DIS
1
2
R59
10KR2J-3-GP
DY
R59
10KR2J-3-GP
DY
1
2
R1204
4K7R2F-GP
DY
R1204
4K7R2F-GP
DY
1
2
C790
S
C
D
0
1U
50V
2K
X
-1G
P
DIS
C790
S
C
D
0
1U
50V
2K
X
-1G
P
DIS
1
2
R63
10KR2J-3-GP
DIS
R63
10KR2J-3-GP
DIS
1
2
R432
100R
2F
-L1-
G
P
-U
DIS
R432
100R
2F
-L1-
G
P
-U
DIS
DQB_0
C5
DQB_1
C3
DQB_10
J4
DQB_11
K6
DQB_12
K5
DQB_13
L4
DQB_14
M6
DQB_15
M1
DQB_16
M3
DQB_17
M5
DQB_18
N4
DQB_19
P6
DQB_2
E3
DQB_20
P5
DQB_21
R4
DQB_22
T6
DQB_23
T1
DQB_24
U4
DQB_25
V6
DQB_26
V1
DQB_27
V3
DQB_28
Y6
DQB_29
Y1
DQB_3
E1
DQB_30
Y3
DQB_31
Y5
DQB_32
AA4
DQB_33
AB6
DQB_34
AB1
DQB_35
AB3
DQB_36
AD6
DQB_37
AD1
DQB_38
AD3
DQB_39
AD5
DQB_4
F1
DQB_40
AF1
DQB_41
AF3
DQB_42
AF6
DQB_43
AG4
DQB_44
AH5
DQB_45
AH6
DQB_46
AJ4
DQB_47
AK3
DQB_48
AF8
DQB_49
AF9
DQB_5
F3
DQB_50
AG8
DQB_51
AG7
DQB_52
AK9
DQB_53
AL7
DQB_54
AM8
DQB_55
AM7
DQB_56
AK1
DQB_57
AL4
DQB_58
AM6
DQB_59
AM1
DQB_6
F5
DQB_60
AN4
DQB_61
AP3
DQB_62
AP1
DQB_63
AP5
DQB_7
G4
DQB_8
H5
DQB_9
H6
MVREFDB
Y12
MVREFSB
AA12
TESTEN
AD28
CASB0#
W10
CASB1#
AA10
CKEB0
U10
CKEB1
AA11
CLKB0
L9
CLKB0#
L8
CLKB1
AD8
CLKB1#
AD7
CLKTESTA
AK10
CLKTESTB
AL10
CSB0_0#
P10
CSB0_1#
L10
CSB1_0#
AD10
CSB1_1#
AC10
DQMB_0
H3
DQMB_1
H1
DQMB_2
T3
DQMB_3
T5
DQMB_4
AE4
DQMB_5
AF5
DQMB_6
AK6
DQMB_7
AK5
DRAM_RST
AH11
MAB_0
P8
MAB_1
T9
MAB_10
AC8
MAB_11
AC9
MAB_12
AA7
MAB_13/BA2
AA8
MAB_14/BA0
Y8
MAB_15/BA1
AA9
MAB_2
P9
MAB_3
N7
MAB_4
N8
MAB_5
N9
MAB_6
U9
MAB_7
U8
MAB_8
Y9
MAB_9
W9
ODTB0
T7
ODTB1
W7
RASB0#
T10
RASB1#
Y10
QSB_0/RDQSB_0
F6
QSB_1/RDQSB_1
K3
QSB_2/RDQSB_2
P3
QSB_3/RDQSB_3
V5
QSB_4/RDQSB_4
AB5
QSB_5/RDQSB_5
AH1
QSB_6/RDQSB_6
AJ9
QSB_7/RDQSB_7
AM5
QSB_0B/WDQSB_0
G7
QSB_1B/WDQSB_1
K1
QSB_2B/WDQSB_2
P1
QSB_3B/WDQSB_3
W4
QSB_4B/WDQSB_4
AC4
QSB_5B/WDQSB_5
AH3
QSB_6B/WDQSB_6
AJ8
QSB_7B/WDQSB_7
AM3
WEB0#
N10
WEB1#
AB11
MEMORY INTERFACE B
4 OF 8
AVGA1D
M92-M2-GP
DIS
MEMORY INTERFACE B
4 OF 8
AVGA1D
M92-M2-GP
DIS
1
2
R56
10KR2J-3-GP
DY
R56
10KR2J-3-GP
DY
1
2
R378
10KR2J-3-GP
DIS
R378
10KR2J-3-GP
DIS
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