PCM-MIO-A-1/Software Summary
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logic. The following table summarizes the registers, and the text that
follows provides details on each of the internal registers.
8.3.2 Register Details
Port 0 through 5 I/O
Each I/O bit in each of the six ports can be individually programmed for
input or output. Writing a
0
to a bit position causes the corresponding
output pin to go to a high-impedance state (pulled high by external 10 K
Ω
resistors). This allows it to be used as an input. When used in the input
mode, a read reflects the inverted state of the I/O pin, such that a high on
the pin reads as a
0
in the register. Writing a
1
to a bit position causes that
output pin to sink current (up to 12 mA), effectively pulling it low.
INT_PENDING
This read-only register reflects the combined state of the
INT_ID0
through
INT_ID2
registers. When any of the lower three bits are set, it indicates
that an interrupt is pending on the I/O port corresponding to the bit
position(s) that are set. Reading this register allows an Interrupt Service
Routine to quickly determine if any interrupts are pending and which I/O
port has a pending interrupt.
PAGE/LOCK
This register serves two purposes. The upper two bits select the register
page in use as shown here.
Bits 5 through 0 allow for locking the I/O ports. A
1
written to the I/O port
position prohibits further writes to the corresponding I/O port.
BASE+ I/O Address Offset
Page 0
Page 1
Page 2
Page 3
16 00h
Port
0
I/O
17 01h
Port
1
I/O
18 02h
Port
2
I/O
19 03h
Port
3
I/O
20 04h
Port
4
I/O
21 05h
Port
5
I/O
22 06h
Int_Pending
23 07h
Page/Lock
24 08h IRQ_REG
Pol_0
Enab_0
Int_ID0
25 09h REV_LO
Pol_1
Enab_1
Int_ID1
26 0ah REV_HI
Pol_2
Enab_2
Int_ID2
D7
D6
Page
0
0
Page
0
0
1
Page
1
1
0
Page
2
1
1
Page
3
