ITX-F-3800/Configuration
v1.0
www.winsystems.com
Page 15
Matching Connectors
•
JST B10B-PHDSS
Cable Housing
•
JST PHDR-10VS
7.4.6 eDP1 - eDP Interface
eDP1: eDP connector (2x10 pin, 1.25 mm)
Layout and Pin Reference
Matching Connectors
•
Hirose DF13-20DP-1.25V
Cable Housing
•
Hirose DF13-20DS-1.25C
7.4.7 DIO - Digital Input/Output
DIO: Digital input/output 0-3 connector (2x5 pin, 2.0 mm)
eDP1
Pin
Description
Pin
Description
1
Lane-0-DATA-
2
+12V or +5V
3
Lane-0-DATA+
4
+12V or +5V
5
Lane-1-DATA-
6
GND
7
Lane-1-DATA+
8
GND
9
Backlight enable
10
GND
11
PWM dimming for
eDP
12
GND
13
I
2
C data
14
+LCD (5V or 3.3V)
15
I
2
C clock
16
+LCD (5V or 3.3V)
17
eDP Aux+
18
+LCD (5V or 3.3V)
19
eDP Aux-
20
GND
Notes:
1. The eDP interface supports 2 lanes.
2. JVL1: eDP panel +5V/+3.3V (default) voltage select.
3. eDP1 PIN 9 for panel backlight enable. +5V level.
4. eDP1 PIN 11 for panel backlight dimming control.
5. eDP1 pins 2 and 4 backlight power default set +5V.
pin 1