Panel Specification
1
T
vp
T
vda
T
vdb
INPUT SIGNAL TIMING DIAGRAM
Valid display data (1024 Tck)
Tckh
T
hde
T
ch
T
ck
DCLK
DATA
T
sde
T
hd
T
sd
DE
T
hdb
DCLK
Invalid
Valid
DATA
T
hp
T
hda
0.3VDD
0.5VDD
2
768
768
DE
0.7VDD
0.3VDD
DE
Tckl
0.7VDD
0.7VDD