winsonic MCH1505S-XN25C, Руководство пользователя, Страница: 14 / 30

Panel Specification
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Parameter Symbol Min Typ Max Unit Remarks
Pixel clock Frequency Fck - 65 80 MHz
Pixel clock period Tck 12.5 15 20 ns
Duty ratio (%Tch) - 45 50 55 % Tch/Tck
s n - - 5 h k c T e m it h g i H
DCLK
s n - - 5 l k c T e m it w o L
s n - - 4 d s T e m it p u t e S
s n - - 4 d h T e m it d l o H
s n - - 4 e d s T e m it p u t e S
DATA
DE
s n - - 4 e d h T e m it d l o H
Vertical Frequency Fv - 60 75 Hz
Vertical display active period Tvda 768 768 768 Thp
Vertical display blank period Tvdb 1 38 - Thp
Vertical
Vertical period Tvp 769 806 - Thp
Horizontal display active
period
Thda 1024 1024 1024 Tck
Horizontal display blank period Thdb 76 320 776 Tck
Horizontal
Horizontal period Thp 1100 1344 1800 Tck
Note (1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
to low logic level or ground. Otherwise, this module would operate abnormally.