RS-232 REMOTE OPERATION
WJ-8711A DIGITAL HF RECEIVER
4-20
4.6
RECEIVER STATUS SUMMARY
Figure 4-1
illustrates the architecture of the receiver's status registers. It is composed of six
eight-bit registers and one 16-bit register, whose logic gating allows the programmer great flexibility in remote
operations. The eight bit registers can be split into three pairs. Each pair consists of a status register and an
enable register.
One pair is composed of the Event Summary Status Register (whose functions are summarized
in
paragraph 4.6.2
) and the Event Summary Status Enable Register. Each bit in the Event Summary Status
Register is logically ANDed to a bit in the Event Summary Status Enable Register. The ANDed combination
of these two registers are logically ORed to set the Event Summary Status Bit (ESB) of the Status Byte
Register. The Device-Dependent Error Bit (DDE) of the Event Summary Status Register is the ORed
combination of the 16-bit Device-Dependent Error Register (see
paragraph 4.6.4
).
The second pair is composed of the Status Byte Register and the Service Request Enable
Register. The receiver uses only three bits of the Status Byte Register as described in
Table 4-3
. The ANDed
combination of bits 0 and 5 of the Status Byte Register and the Service Request Enable Register are logically
ORed to determine the setting of bit six (RQS) of the Status Byte Register. If the RQS bit is set high, a service
request is asserted.
Table 4-3. Status Byte Register, Bit Evaluation
Bit
Number
Mnemonic
Description
0
RSB
Receiver Status Bit
- This bit, when set,
indicates that an event has caused a bit or bits in
the Receiver Status Register to be set (see
paragraph 4.6.3
). This bit is cleared by *CLS
or by reading the contents of the Receiver Status
Register using the RSR? query.
1-4
Not Used
5
ESB
Event Summary Bit
- This bit, when set,
indicates that the Event Summary Status Register
has set SRQ. By reading the Event Summary
Status Register via the *ESR? mnemonic, the
host controller may identify what status event has
caused the SRQ. This bit is cleared by sending,
*CLS or reading the contents of the Event Status
Register.
6
RQS
Request Service Bit
- This bit, when set,
indicates that the unit has asserted SRQ.
7
Not Used
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Содержание WJ-8711A
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