Watkins-Johnson Company WJ-8711A, Инструкция по установке, эксплуатации и обслуживанию

Страница: 153 / 261

WJ-8711A DIGITAL HF RECEIVER CIRCUIT DESCRIPTION
6-9
The Control and Interface Section directs the operation of the Type 797006 RF Assembly
(A3) and it directs the operation of the functions performed by the Digital Signal Processing Section,
contained on this assembly.
The heart of the Control and Interface Section is the 68HC11 microcontroller. It continuously
monitors the receiver functions and provides control data to direct its operation. On receiver power up, the
control processor enters into a power up routine that checks the two banks of configuration switches to
properly configure the external control interfaces for communication with external controlling devices, and it
performs a built-in-test (BITE) operation to verify proper operation of key receiver parameters. Once the
configuration and testing have been completed, the microcontroller then directs control data to the RF
Assembly and the Digital Signal Processing section to set the receiver parameters for operation. The
communication with the Digital Signal Processing section is via the microcontroller's address and data buses.
It consists of data that determines the parameters that the Digital Signal Processor uses in processing of the
tuned signal.
The transfer of control data to the RF section is performed through a ribbon cable connected
at J4. This data (RF DATA) is transferred serially as a sequence of 8-bit data words, via J4 pin 10, and
provides the data to five control registers in the RF Assembly that: phase locks the receiver time base; tunes
the RF Assembly to the desired frequency; and selects the NORMAL, PREAMPLIFIED, or ATTENUATED
RF Input Path. Three control lines (RF0, RF1, and RF2) are set as each data word is transferred, determining
the destination of the data after it reaches the RF Assembly. These control lines form a three bit address via
pins 9, 8, and 7 of J4, respectively, which are decoded by the RF Assembly to properly direct the data transfer
(refer to Table 6-1). The RF DATA, and the RF0, RF1, and RF2 Control lines are synchronized with the RF
clock (RFCLK), J4 pin 11. This is a sequence of 8 bit clock bursts that provide timing for the data transfer.
Three status lines, provided via connector J4, are monitored by the Control Section to
determine the operating status of the RF assembly. They are routed to a receiver status input register, and are
checked periodically to verify proper operation and to determine if any control action is to be taken. The
RFERR status line provides a logic level to notify the Control section if an error condition occurs. With an
external reference connected to the receiver rear panel, and, with all of the phase-locked-loop synthesizers in
the RF Assembly locked and operating normally, the RFERR line provides a constant logic "1". If any of the
synthesizers fail, the unlocked synthesizer causes a logic "0". If no external reference is connected to the
receiver rear panel, the internal reference is active, and logic "0" pulses occur at intervals of approximately 8
msec. Also, if the receiver is equipped with the RF Preselector option, a signal overload will result in a logic
"0" on the RFERR line.
The Control and Interface section timing is synchronized with the receiver's time base by a
40 MHz signal, provided by the RF Assembly via J4 pin 23. This signal enters the synchronized clock
distribution circuitry of the Control and Interface section, where it is used to generate an 8 MHz clock for the
microcontroller, a 2 MHz clock to provide timing for transferring control data to the RF Assembly, and the
12.8 MHz clock for timing of the analog-to-digital conversion in the IF digitizer.
Three methods of control of the receiver operation are supported by the Control and Interface
section. The RS-232 interface provides a communications link from the microcontroller to a 25 pin RS-232
connector at the receiver rear panel (A2J3). This is a three wire configuration that permits talk and listen
capabilities, using RS-232 levels. The CSMA interface provides limited receiver control capabilities. The
second form of receiver control is via the Control Interface output (A2J7). This interface is routed to the Front
Panel Assembly circuit card via a 24 conductor ribbon cable attached to A1A1E7.
Courtesy of http://BlackRadios.terryo.org