AWARD BIOS SETUP
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SDRAM CAS Latency Time : When synchronous DRAM is installed, the number of
clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
DRAM Data Integrity Mode : Select Parity or ECC (error-correcting code), according to
the type of installed DRAM.
System BIOS Cacheable : Selecting Enabled allows caching of the system BIOS ROM
at F0000h-FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result.
Video BIOS Cacheable : Selecting Enabled allows caching of the video BIOS ROM at
C0000h to C7FFFh, resulting in better video performance. However, if any program
writes to this memory area, a system eror may result.
Video RAM Cacheable : Selecting Enabled allows caching of the video BIOS ROM at
C0000h to C7FFFh, resulting in better video performance. However, if any program
writes to this memory area, a memory access error may result.
8/16 Bit I/O Recovery Time : The I/O recovery mechanism adds bus clock cycles
between PCI-originated I/O cycles to the ISA bus. This delay takes place because the
PCI bus is so much faster than the ISA bus. These two fields let you add recovery time
(in bus clock cycles) for 16-bit and 8-bit I/O.
Memory Hole At 15M-16M : The default setting is “Disabled”. Set to “Enabled” when
the system memory size is equal to or greater than 16M bytes, then the physical memory
address from 15M to 16M will be passed to PCI or ISA. Thus, there will be 1M Bytes
hole in your system memory. This option is designed for some OS with special add-on
cards which need 15M-16M memory space.
Passive Release : The default setting is “Enabled”. When Enabled, CPU to PCI bus
accesses are allowed during passive release. Otherwise, the arbiter only accepts
another PCI master access to local DRAM.
Delayed Transaction : The default setting is “Disabled”. The chipset has an
embedded 32-bit posted write buffer to support delay transactions cycles. Select
Enabled to support compliance with PCI specification version 2.1.
