Clock Re-Generator Functional Block Diagram
FIG3-2 Clock Re-Generator
ADC Block Description
Variable Gain Amplifier (VGA)
The front-end circuit is designed to provide four major functions:
Provide AC coupled interface with single-ended R/G/B input signal, convert single-ended signal to
differential signal, and define common mode voltage.
Define CLAMPING voltage level with respect to ground for image brightness control.
Perform user programmable precision gain amplification.
Provide low impedance differential driver for ADC.
Phase Locked Loop (PLL) and Multi-Phase Generation
The phase locked loop (PLL) generates desired ADC sampling clock frequency (30 MHz to 80 MHz) from
external line clock CKREF. The exact frequency is register programmable and related to the input line clock
CKREF as follows:
Freq (PLL) = Freq (CKREF)* Ndiv <12:0>
To ease the graphic interface, a phase programmable output clock is also generated for external use. The exact
phase delay with respect to VCO output clock is register programmable and can be formulated as follows:
T
DELAY
=
IJ
+Tclk * phase<4:0> / 32
Where
there
is a systematic delay. Due to the periodic nature of the clock, user can practically program the ADC
sampling anywhere with respect to data in the step size of Tclk/32.
ADC
Based on the requirements for this ADC (high speed, low power and small size). The sub ranging architecture is
used to minimize the number of comparators. The interpolation technique is also used to reduce the number of
preamplifiers. Two identical 8bit ADC converters are used to increase the throughput of sub ranging ADC to one
conversion per clock cycle.
Each ADC operates in two-step sub range, i.e. coarse (3 bits) and fine (5 bits). One to four interpolations is
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5
0m
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performed in fine conversion step to minimize the number of preamplifier and to improve differential non-linearity
errors (DNL). In addition, in order to prevent potential error occurred during coarse conversion, digital error
correction technique is also used.
Содержание VG150m-1
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