VIA EPIA-M920 User Manual
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6.7.1.
DRAM Configuration
The DRAM Configuration screen has two features for controlling the system DRAM. All other DRAM
features are automated and cannot be accessed.
Figure 63: Illustration of DRAM Configuration screen
6.7.1.1.
DRAM Clock
The DRAM Clock option enables the user to determine how the BIOS handles the memory clock
frequency. The memory clock can either be dynamic or static. This feature has eleven options.
By SPD
By SPD option enables the BIOS to select a compatible clock frequency for the installed memory.
400MHz
The 400MHz option forces the BIOS to be fixed at 800MHz for DDR3 memory modules.
533MHz
The 533MHz option forces the BIOS to be fixed at 1066MHz for DDR3 memory modules.
566MHz
The 566MHz option forces the BIOS to be fixed at 1132MHz for DDR3 memory modules.
600MHz
The 600MHz option forces the BIOS to be fixed at 1200MHz for DDR3 memory modules.
633MHz
The 633MHz option forces the BIOS to be fixed at 1266MHz for DDR3 memory modules.
667MHz
The 667MHz option forces the BIOS to be fixed at 1334MHz for DDR3 memory modules.
700MHz
The 700MHz option forces the BIOS to be fixed at 1400MHz for DDR3 memory modules
733MHz
The 733MHz option forces the BIOS to be fixed at 1466MHz for DDR3 memory modules
766MHz
The 766MHz option forces the BIOS to be fixed at 1532MHz for DDR3 memory modules
800MHz
The 800MHz option forces the BIOS to be fixed at 1600MHz for DDR3 memory modules
6.7.1.2.
VGA Share Memory (Frame Buffer)
The VGA Share Memory feature enables the user to choose the amount of the system memory to reserve
for use by the integrated graphics controller. The selections of memory amount that can be reserved are
256MB and 512MB.
