Chapter 2
20
2.8
JP20 - CPU CLOCK DELAY
JP20 is for the CPU Clock Delay setting. Refer to Fig 2 for JP20 location.
JP20 -- CPU Clock Delay
2.9
JP5, JP6, JP7 - CPU FREQUENCY CONFIGURATION
JP5, JP6, & JP7 are for the CPU Frequency Configuration. Two different settings are provided for
different Clock Generator that is used at U16 or U17. Refer to Fig 2 for the location of U16/U17 and
jumpers.
JP5, JP6, JP7-- CPU Frequency Configuration
Note:
Winbond W83C17 and UMC U59515-01 are pin to pin compatible to MX-8315 and
PhaseLink PLL52C08-01 is pin to pin compatible to AV9107-03.
Table 7
Table 8
Содержание GMB-486SG
Страница 1: ...GMB 486SG High Performance 486 VLB Motherboard User s Manual For GMB 486sg v2 Manual Edition 6 03 ...
Страница 12: ...Hardware Configuration 7 Table 1C CPU Type P24C DX4 OPTIONAL Table 1D CPU Type 486SX SLE 486SX ...
Страница 13: ...Chapter 2 8 Table 1E CPU Type 486DX DX2 SLE 486DX DX2 Table 1F CPU Type Cyrix 486S ...
Страница 14: ...Hardware Configuration 9 Table 1G CPU Type Cyrix 486DX DX2 Table 1H CPU Type UMC U5SX 486 ...
Страница 17: ...Chapter 2 12 Table 1M CPU Type Cx486DX2 V80 4 0V Optional Table 1N CPU Type Cx5x86 IBM 486 4V3100GIC 3 3V ...
Страница 33: ...Chapter 3 28 3 3 1 CONNECTIONLOCATIONS Fig 7 Connector Locations ...