VESTEL DVD4250D, DVD-плеер

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has sufficient bandwidth to support the decoding and displaying of CCIR1656/601 resolution images at full
fra me rate.
7 FLASH M
EMORY
The decoder board supports AMD class Flash memories. Currently 4 configurations are supported:
FLASH_512K_8b
FLASH_1024K_8b
FLASH_512Kx2_8b
FLASH_512Kx2_16b
The Vibratto II permits both 8- and 16-bit common memory I/O accesses with a removable storage card via the
host interface.
8 S
ERIAL
EEPROM M
EMORY
An I2C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup,
etc.) and software configuration.. Industry standard EEPROM range in size from 1kbit to 256kbit and share the
same IC footprint and pinout. The default device is 2kbit, 256kx 8, SOIC8 SGS Thomson ST24C02M1 or
equivalent.
9 A
UDIO
I
NTERFACE
A
UDIO
S
AMPLING
R
ATE AND
PLL C
OMPONENT
C
ONFIGURATION
The ES66x8 Vibratto II audio mode configuration is selectable, allowing it to interface directly with
low-cost audio DACs and ADCs. The audio port provides a standard I
2
S interface input and output and S/PDIF
(IEC958) audio output. Stereo mode is in I
2
S format while six channels Dolby Digital (5.1 channel) audio output
can be channeled through the S/PDIF. The S/PDIF interface consists of a bi-phase mark encoder, which has low
skew. The transmit I
2
S interface supports the 128, 192, 256, 384, and 512 sampling frequency formats, where
sampling frequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz. The audio samples for the I
2
S
transmit interface can be 16, 18, 20, 24, and 32-bit samples.
For Linear PCM audio stream format, the Vibratto II supports 48 kHz and 96 kHz. Dolby Digital audio
only supports 48 kHz. The ES6008/18 Vibratto II incorporates a built-in programmable analog PLL in the device
architecture in order to generate a master audio clock. The MCLK pin is for the audio DAC clock and can either
be an output from or an input to the ES66x8 Vibratto II . Audio data out (TSD) and audio frame sync (TWS) are
clocked out of the Vibratto II based on the audio transmit bit clock (TBCK). Audio receive bit clock (RBCK) is
used to clock in audio data in (RSD) and audio receive frame sync (RWS).
10 F
RONT
P
ANEL
10.1 VFD C
ONTROLLER
The VFD controller is a PTC PT6311. This controller is not a processor, but does include a simple state
machine which scans the VFD and reads the front panel button matrix. The 6311 also includes RAM so it can
store the current state of all the VFD icons and segments. Therefore, the 6311 need only be accessed when the
VFD status changes and when the button status is read. The ES66x8 can control this chip directly using PIO pins
or can allow the front panel PIC to control the VFD.
11 M
ISCELLANEOUS
F
UNCTIONS
11.1 R
ESET
C
IRCUITRY
Two different chips are supported to provide the power-on-reset and pushbutton reset function:
AAT3521 or V6300.