23
32” TFT TV Service Manual
06/03/2006
NC (Pin 3)
No connection.
V
DD
(Pin 4)
This is the +5V power pin for the chip.
HSYNC (Pin 5)
This pin inputs a horizontal synchronize signal. It is negative polarity by default. The leading edge of
HSYNC synchronizes its internal horizontal timing. The maximum input ratio between PIXin/HSYNC should
not greater than 1580 for displaying 12X18 font matrix. For displaying 10X18 font matrix, this ratio should
not greater than 1280.
RESET (Pin 6)
An active low signal will reset ROW15 and ROW16 control registers. Refer to Control Registers section for
default set-tings. A proper RC network have to be tighten to this pin to ensure the device initialize properly
during power up. Refer to the application diagram.
SDA (Pin 7)
Data and control message are being transmitted to this chip from a host MCU via M_bus systems. This
wire is configurated as a uni-directional data line. (Detailed description of protocols will be discussed in the
M_BUS section).
SCL (Pin 8)
A separate synchronizing clock input from the transmitter is required for M_Bus protocol. Data is read at
the rising edge of each clock signal.
V
DD
(Pin 9)
This is the power pin for the digital logic of the chip.
VSYNC (Pin 10)
Similar to Pin 5, this pin inputs a vertical synchronize signal to synchronize the vertical control circuit. It is
negative polarity by default.
V
DD
(I) (Pin 11)
This is the voltage supply of RGB outputs when low intensity of Windows/ROW is selected. The RBG
output level would be equal to VDD(I) in this case. Please refer to Row Attribute/Window registers for more
detail. The input voltage for this pin should be equal to or less than V DD (Pin 17) for normal operation.
FBKG (Pin 12)
This pin will output a logic high while displaying characters or windows. It is defaulted to high impedance
state after power on, or when there is no output. An external 10
κΩ
resistor pulled low is recommended to
avoid level toggling caused by hand effect when there is no output.
B,G,R (Pin 13, 14, 15)
LMOSD2-16 color outputs in CMOS level to the host monitor. These three signals are open drain outputs if
3_STATE bit is set and the color intensity is inactive. Otherwise, they are active high push-pull outputs.
See “REGISTERS” for more information. These pins are in high impedance state after power on.
V
SS
(Pin 24)
This is the ground pin for the digital logic of the chip.
