Vertex Standard VX-210AU, Руководство по обслуживанию

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10
Circuit Description
of output power.
The transmit signal then passes through the antenna switch
D1007 (
RLS135
) and is low-pass filtered to suppress har-
monic spurious radiation before delivery to the antenna.
3-1 Automatic Transmit Power Control
RF power output from the final amplifier is sampled
by C1099, and is rectified by D1029 (
1SS321
). The result-
ing DC is fed back through Q1027 (
FMW1
) to the drive
amplifier Q1016 and final amplifier Q1021, for control of
the power output.
The microprocessor selects “High” or “Low” power lev-
els.
3-2 Transmit Inhibit
When the transmit PLL is unlocked, pin 7 of PLL chip
Q1004 goes to a logic “low.” The resulting DC unlock con-
trol voltage is passed to pin 24 of the microprocessor
Q1014. While the transmit PLL is unlocked, pin 22 of
Q1014 remains high, which then turns off Q1031 and the
Automatic Power Controller Q1027 (
FMW1
) to disable the
supply voltage to the drive amplifiers Q1012 and Q1016
and final amplifier Q1021, thereby disabling the transmit-
ter.
3-3 Spurious Suppression
Generation of spurious products by the transmitter is min-
imized by the fundamental carrier frequency being equal
to final transmitting frequency, modulated directly in the
transmit VCO. Additional harmonic suppression is pro-
vided by a low-pass filter consisting of L1003, L1006, and
L1007 plus C1002, C1007, C1013, C1017, C1022, and C1169,
resulting in more than 60 dB (High Power) of harmonic
suppression prior to delivery to the antenna.
4. PLL Frequency Synthesizer
The PLL circuitry on the Main Unit consists of VCO
Q1005 (
2SK508-K52
), VCO buffer Q1008 (
2SC5005
), and
PLL subsystem IC Q1004 (
MB15A01FV1
), which contains
a reference divider, serial-to-parallel data latch, program-
mable divider, phase comparator and charge pump.
Stability is maintained by a regulated 3.5 V supply, via
Q1040 (
TK11235BMCL
) and R1019/R1020, temperature
compensating thermistors TH1001, TH1002, and TH1003,
and varactor diode D1004 (
1SV230
), which is associated
with the 14.50 MHz frequency reference crystal X1001.
While receiving, VCO Q1005 oscillates between 406.05
and 441.05 MHz according to the transceiver version and
the programmed receiving frequency. The VCO output is
buffered by Q1008, then applied to the prescaler section
of Q1004. There the VCO signal is divided by 64 or 65,
according to a control signal from the data latch section of
Q1004, before being sent to the programmable divider sec-
tion of Q1004.
The data latch section of Q1004 also receives serial di-
viding data from the microprocessor Q1014, which caus-
es the pre-divided VCO signal to be further divided in
the programmable divider section, depending upon the
desired receive frequency, so as to produce a 5 kHz or
6.25 kHz derivative of the current VCO frequency.
Meanwhile, the reference divider section of Q1004 di-
vides the 14.5 MHz crystal reference from the reference
oscillator Q1004, by 2900 (or 2320) to produce the 5 kHz
(or 6.25 kHz) loop reference (respectively).
The 5 kHz (or 6.25 kHz) signal from the programmable
divider (derived from the VCO) and that derived from
the reference oscillator are applied to the phase detector
section of Q1004, which produces a pulsed output with
pulse duration depending on the phase difference between
the input signals.
This pulse train is filtered to DC and returned to the
varactor D1001 (
HVC355B
) and D1002 (
HVC355B
).
Changes in the level of the DC voltage applied to the var-
actor affect the reference in the tank circuit of the VCO
according to the phase difference between the signals de-
rived from the VCO and the crystal reference oscillator.
The VCO is thus phase-locked to the crystal reference
oscillator. The output of the VCO Q1005, after buffering
by Q1008 and amplification by Q1009, is applied to the
first mixer as described previously.
For transmission, the VCO Q1005 oscillates between 450
and 485 MHz according to the model version and pro-
grammed transmit frequency. The remainder of the PLL
circuitry is shared with the receiver. However, the divid-
ing data from the microprocessor is such that the VCO
frequency is at the actual transmit frequency (rather than
offset for IFs, as in the receiving case). Also, the VCO is
modulated by the speech audio applied to D1005
(
HVU350
), as described previously.
Receive and transmit buses select which VCO is made
active by Q1002 (
RT1N441U
).
5. Miscellaneous Circuits
5-1 Push-To-Talk Transmit Activation
The PTT switch on the microphone is connected to pin
35 of microprocessor Q1014, so that when the PTT switch
is closed, pin 23 of Q1014 goes low. This signal disables
the receiver by disabling the 5 V supply bus at Q1035
(
DTB123EK
) to the front-end, FM IF subsystem IC Q1036,
and the receiver’s VCO circuitry.
At the same time, Q1026 (
FMW1
) and Q1031 (
2SB1122S
)
activate the transmit 5V supply line to enable the trans-
mitter.