Vertex Standard VX-160EU, Руководство по обслуживанию

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12
Automatic Transmit Power Control
Current from the final amplifier is sampled by R1020,
R1039, and R1042, and is rectified by Q1003 ( IMZ2A
T108 ). The resulting DC is fed back through Q1002
( FMW1 T98 ) to the drive amplifier Q1009 ( 2SK2973 )
and final amplifier Q1006 ( 2SK2974 ), for control of the
power output.
The microprocessor selects “High” or “Low” power
levels.
Transmit Inhibit
When the transmit PLL is unlocked, pin 7 of PLL chip
Q1050 (
MB15A02PFV1-G-BND-EF
) goes to a logic
“Low,” and unlock detector Q1051 ( 2SA1602A-F ) goes
to a logic “High.” The resulting DC unlock control volt-
age is passed to pin 14 of the microprocessor, Q1011
(
M37516F8HP ). While the transmit PLL is unlocked, pin
22 of Q1011 remains high, which then turns off Q1023
(
CPH6102-TL ) to disable the TX 5 V line to Q1014
( 2SC3357-T2 ) and Q1020 ( 2SC5005-T1 ), and also Au-
tomatic Power Controller Q1002 ( FMW1 T98 ) the con-
trols the bias voltage for Q1006 ( 2SK2974 ) and Q1009
( 2SK2973-T13 ), thereby disableing the transmitter.
Spurious Suppression
Generation of spurious products by the transmitter is
minimized by the fundamental carrier frequency being
equal to final transmitting frequency, modulated directly
in the transmit VCO. Additional harmonic suppression is
provided by a low-pass filter consisting of coils L1001,
L1002, and L1003 plus capacitors C1001, C1002, C1010,
C1012, C1013, C1014, C1015, and C1016, resulting har-
monic suppression prior to delivery to the antenna.
PLL Frequency Synthesizer
The PLL circuitry on the Main Unit consists of VCO
Q1037 ( 2SK508-K52 ), and Q1040 ( 2SC4227-R34 ),
VCO buffer Q1025 ( 2SC5005 ), and PLL subsystem IC
Q1050 ( MB15A02PFV1-G-BND-EF ), which contains
a reference divider, serial-to-parallel data latch, program-
mable divider, phase comparator, and charge pump.
Frequency stability is maintained by temperature com-
pensating thermistor TH1001. The output from TH1001
is applied to pin 39 of Q1011 (
M37516F8HP ). Q1011
outputs thermal data to D/A converter Q1004 (
M62364FP
600D ), which produces a DC voltage corresponding to
the thermal data. The resulting DC voltage is applied to
varactor diode D1031 (
HVC350B TRF ) to stabilize the
14.60 MHz Reference Frequency.
While receiving, VCO Q1037 oscillates between 395.75
and 425.75 MHz according to the transceiver version and
the programmed receiving frequency. The VCO output is
buffered by Q1025 , then applied to the prescaler section
of Q1050. There the VCO signal is divided by 64 or 65,
according to a control signal from the data latch section of
Q1050, before being sent to the programmable divider
section of Q1050.
The data latch section of Q1050 also receives serial di-
viding data from the microprocessor, Q1011, which causes
the pre-divided VCO signal to be further divided in the
programmable divider section, depending upon the desired
receive frequency, so as to produce a 5.0 kHz or 6.25 kHz
derivative of the current VCO frequency.
Meanwhile, the reference divider section of Q1050 di-
vides the 14.60 MHz crystal reference (from the reference
oscillator) by 2920 (or 2336) to produce the 5 kHz (or
6.25 kHz) loop references (respectively).
The 5 kHz (or 6.25 kHz) signal from the programmable
divider (derived from the VCO) and that derived from the
reference oscillator are applied to the phase detector sec-
tion of Q1011, which produces a pulsed output with pulse
duration depending on the phase difference between the
input signals.
This pulse train is filtered to DC and returned to the
varactor D1024, D1025, D1026, and D102
HVC350B TRF ). Changes in the level of the DC voltage
are applied to the varactor, affecting the reference in the
tank circuit of the VCO according to the phase difference
between the signals derived from the VCO and the crystal
reference oscillator.
The VCO is thus phase-locked to the crystal reference
oscillator. The output of the VCO Q1037, after buffering by
Q1025, is applied to the first mixer as described previously.
For transmission, the VCO Q1040 oscillates between
440 and 470 MHz according to the model version and
programmed transmit frequency. The remainder of the PLL
circuitry is shared with the receiver. However, the divid-
ing data from the microprocessor is such that the VCO
frequency is at the actual transmit frequency. Also, the
VCO is modulated by the speech audio applied to D1020
(
HVC350B ), as described previously.
Receive and transmit buses select which VCO is made
active, using Q1027, Q1038 RT1N441U-T11-1 ),
and Q1039 ( RT1P441U-T11-1 ).
Miscellaneous Circuits
Push-To-Talk Transmit Activation
The PTT switch on the microphone is connected to pin
48 of microprocessor Q1011 (
M37516F8HP
), so that
when the PTT switch is closed, pin 23 of Q1011 goes low.
This signal disables the receiver by disabling the 5 V sup-
ply bus at Q1019 (
DTB123EK T146 ) to the front-end,
FM IF subsystem IC Q1048 (
TA31136FN
), and the re-
ceiver VCO circuitry.
At the same time, Q1024 (
FMW1 T98
) and Q1023
( CPH6102-TL ) activate the transmit 5V supply line to
enable the transmitter.
Circuit Description
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