VersaLogic Ocelot, Справочное руководство

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Datasheet of VL-CBR-2012 - 20" 24-BIT LVDS CABLE
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VL-EPMs-21 Reference Manual 46
System Resources and Maps
Memory Map
The lower 1 MB memory map of the VL-EPMs-21 is arranged as shown in the following table.
Various blocks of memory space between A0000h and FFFFFh are shadowed.
Table 19: Memory Map
Start
Address End
Address
Comment
F0000h FFFFFh
System BIOS Area
E0000h EFFFFh
Extended System BIOS Area
C0000h DFFFFh
Expansion Area
A0000h BFFFFh
Legacy Video Area
00000h 9FFFFh
Legacy System Area
I/O Map
The following table lists the common I/O devices in the VL-EPMs-21 I/O map. User I/O devices
should be added using care to avoid the devices already in the map as shown in the following
table.
Table 20: On-Board I/O Devices
I/O Device Standard
I/O
Addresses
Secondary Hard Drive Controller 170h
– 177h
PLED and Product ID Register 1D0h
Revision and Type ID Register 1D1h
Video BIOS and GPI Register 1D2h
WDT and HWM Register 1D3h
PC/104 Block Enable Registers 1D4h
– 1D5h
SPX Registers 1D8h
– 1DDh
PC104 IRQ Enable Registers 1DEh
– 1DFh
Primary Hard Drive Controller 1F0h
– 1F7h
COM4 Serial Port Default 2E8h
– 2EFh
COM2 Serial Port Default 2F8h
–2FFh
Secondary Hard Drive Controller 374h
– 376h
COM3 Serial Port Default 3E8h
– 3EFh
Primary Hard Drive Controller 3F4h
–3F6h
COM1 Serial Port Default 3F8h
– 3FFh
Note:
The I/O port traffic is always present on the LPC bus and care must be taken to
avoid conflicts among on-board devices, PC/104, and SUMIT modules.
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