VersaLogic Ocelot, Справочное руководство

Страница: 37 / 64

Distributor of VersaLogic Corporation: Excellent Integrated System Limited
Datasheet of VL-CBR-2012 - 20" 24-BIT LVDS CABLE
Contact us: sales@integrated-circuit.com Website: www.integrated-circuit.com
Interfaces and Connectors
VL-EPMs-21 Reference Manual 30
LVDS F
LAT
P
ANEL
D
ISPLAY
C
ONNECTOR
The integrated LVDS flat panel display in the VL-EPMs-21 is an ANSI/TIA/EIA-644-1995
specification-compliant interface. It can support up to 24 bits of RGB pixel data plus three bits of
timing control (HSYNC/VSYNC/DE) on the four differential data output pairs. The LVDS clock
frequency ranges from 25 MHz to 112 MHz.
The +3.3V power provided to pins 19 and 20 of J6 is protected by a 1 amp fuse.
See the Connector Location Diagram on page 14 for connector location information.
Table 9: LVDS Flat Panel Display Pinout
J6
Pin
Signal
Name
Function
1 GND Ground
2 NC No Connection
3 LVDSA3 Diff. Data 3 (+)
4 LVDSA3# Diff. Data 3 (
–)
5 GND Ground
6 LVFSCLK0 Differential Clock (+)
7 LVDSCLK0# Differential Clock (
–)
8 GND Ground
9 LVDSA2 Diff. Data 2 (+)
10 LVDSA2# Diff. Data 2 (
–)
11 GND Ground
12 LVDSA1 Diff. Data 1 (+)
13 LVDSA1# Diff. Data 1 (
–)
14 GND Ground
15 LVDSA0 Diff. Data 0 (+)
16 LVDSA0# Diff. Data 0 (
–)
17 GND Ground
18 GND Ground
19 +3.3V Protected Power Supply
20 +3.3V Protected Power Supply
37 / 64
37 / 64