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Datasheet of VL-CBR-2012 - 20" 24-BIT LVDS CABLE
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Interfaces and Connectors
VL-EPMs-21 Reference Manual
40
PC/104 (ISA) Expansion Bus (J9-J10)
The VL-EPMs-21 supports a limited implementation of the PC/104 bus. Be sure to check the
requirements of your PC/104 card against the capabilities listed in this section. The VL-EPMs-21
implements an LPC to ISA bridge. The LPC bus on the VL-EPMs-21 has multiple targets
including the firmware hub, super I/O, optional LPC-based SUMIT add-on cards, and the
onboard CPLD containing the PC/104 bridge, VersaLogic registers, and the SPI controller (see
the figure below). Special care must be taken to avoid resource conflicts between all LPC bus-
based targets (including downstream buses such as PC/104 and SPI) as well as legacy devices
internal to the system controller hub (SCH).
Figure 14. VL-EPMs-21 LPC Bus
PC/104
I/O
C
YCLE
S
UPPORT
I/O cycles are 8-bit by default; 16-bit cycles are supported with the following caveats.
Any PC/104 modules that are 16-bit capable must assert IOCS16#
16-bit cycles are enabled in CMOS Setup
All cycles to a 16-bit module are word-aligned (even addressed)
You cannot mix 8-bit and 16-bit PC/104 cycles to a 16-bit PC/104 module.
Intel
System Controller Hub
(SCH)
Firmware Hub
(FWH)
Super I/O
SUMIT A
CPLD
—
LPC-to-PC/104
Bridge
VersaLogic
Registers
SPI Controllers
LPC Bus
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