
Appendix C ____________________________________________________________ List of Signals
VAISALA _______________________________________________________________________ 49
HDRD#
Hard disk read
HDRDR#
Hard disk read from resistor
HDRDY
Hard disk ready
HDRDYR
Hard disk ready from resistor
HDRQ
Hard disk request
HDRQR
Hard disk request from resistor
HDWR#
Hard disk write
HDWRR#
Hard disk write from resistor
I/O Input/
output
IC Integrated
circuit
INA3CP
Serial data 3 output A from buffer
INTA# Interrupt
acknowledge
IOCHCK
I/O channel check
IOCHRDY
I/O channel ready
IOCS16#
Select 16 bit I/O bus
IORD#
I/O bus read
IOWR#
I/O bus write
IP1...2P
Input 1...2 from buffer
IPX1...2 Input
1...2
IRDY#
PCI initiator ready
IRQ1...15
Interrupt request 1...15
ISA Industry
standard
architecture
JTAG
Joint testability action group
JTCK
JTAG test clock in
JTCKIN
JTAG test clock input
JTDI
JTAG test data in
JTDIN
JTAG test data input
JTDO
JTAG test data out
JTDOUT
JTAG test data output
JTDOUTR
JTAG test data output from resistor
JTMS
JTAG test mode select
JTMSIN
JTAG test mode input
KBCLK Keyboard
clock
KBCLKR
Keyboard clock from resistor
KBDATA Keyboard
data
KBDATAR
Keyboard data from resistor
LED
Light Emitting Diode
Mbps
Mega bits per second
MCOL
Ethernet switch collision detect
MEMCS16#
Memory chip select 16
MEMRD# Memory
read
MEMWR# Memory
write
MRES# Master
reset
MRXD0...3
Receive data bit 0 - 3
MSCLK Mouse
clock
MSDATA Mouse
data
OCCLK Oscillator
clock
OCPD# Oscillator
power-down
OCR0...6 Frequency
setting input R0...6
Содержание MPU112
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