Vaisala MPU112, Техническое описание, Страница: 19 / 55

Chapter 5 ____________________________________________ External Communication Interfaces
VAISALA _______________________________________________________________________ 17
- In the 10BaseT Receive operation, the input buffer and level
detecting squelch circuits are employed. A differential input
receiver circuit and a PLL perform the decoding function. The
Manchester-encoded data stream is separated into clock signal and
NRZ data, the PLL locks onto the incoming signal and the KS8995
decodes a data frame.
The PLL clock synthesizer in the KS8995 generates 125, 50, 25 and
10 MHz clocks for internal system timing. Internal clocks are
generated from an external 25 MHz clock input.
The power connections include extensive filtering for the analog
supply voltages.
ARCNET Line Interface
ARCNET Controller D1 contains an internal microsequencer that
performs all of the control operations necessary to carry out the
ARCNET token passing protocol and network configuration.
The processor transmits data by loading the data packed along with its
destination node number into the RAM buffer of the Controller and by
issuing a command to enable the transmitter. First, the Controller
waits for a token, then it sends an enquiry to the destination node. If
the node is free to receive, it responds with an acknowledgment and
the Controller performs the transmit sequence. If the transmit
sequence is completed successfully, the receiving node sends another
acknowledgment to the transmitter and alerts its control processor by
interrupt signal. The processor then reads the received data from the
RAM buffer of the Controller.
Timing signal 20 MHz to D1 comes from oscillator Z2 through PLL
clock multiplier D8. The controller chip D1 is selected with the PCS#
line and its registers are selected for processor access with address
lines PA0, PA1 and PA2. The internal 2-kbyte buffer memory is
accessed indirectly through these registers. PLD D14 PRD# and
PWR# controls determine the data direction on the bus. Interrupt
signal PINT# is connected to the PLD D14.
The controller is connected to the network through the bi-directional
differential Line Transceiver D2. The line is protected against voltage
transients by bi-directional transient suppressors.