SAM-M10Q - Integration manual
Baud rate
Data bits
Parity
Stop bits
921600
8
none
1
Table 10: Possible UART interface configurations
If the amount of data enabled is too much for a certain interface's bandwidth (for example baud
rate of all UBX messages output is 9600 baud), the buffer will fill up. Once the buffer space is
exceeded, new messages to be sent will be dropped. To prevent message loss, the baud rate and
communication speed or the number of enabled messages should be carefully selected so that the
expected number of bytes can be transmitted in less than one second.
2.3.2 I2C
The I2C protocol and electrical interface in SAM-M10Q are fully compatible with Fast-mode of the
I2C industry standard. The interface allows communication with an external host CPU or u-blox
cellular modules with a maximum transfer rate of 400 kb/s. SAM-M10Q operates in slave mode.
The interface stretches the clock when the CPU is busy serving interrupts. The real bit rates
may be slightly lower than the stated maximum transfer rate.
The SCL and SDA pins have internal pull-up resistors which should be sufficient for most
applications. However, depending on the clock speed of the host and the capacitive load on the
I2C lines, additional external pull-up resistors may be necessary. The higher the speed and the
capacitance load, the lower the pull-up resistor needs to be.
Most u-blox receivers are configured by default with the same 7-bit address value (0x42). To poll
or set the I2C slave address, use the CFG-I2C-ADDRESS configuration item (see the u-blox M10
interface description [
]). The CFG-I2C-ADDRESS configuration item is an 8-bit value containing
the I2C slave address in the 7 most significant bits plus a 0 as the least significant bit. Thus, the
default address becomes 0x84(1000 0100).
In designs where the host uses the same I2C bus to communicate with more than one u-
blox receiver, the I2C slave address for each receiver must be configured to a different value.
2.3.2.1 I2C register layout
, there are 256 registers. The data registers 0 to 252, at addresses 0x00 to 0xFC,
contain reserved information and must not be used. Hence, only the last three registers are left for
communication. The registers 0xFD and 0xFE contain the currently available number of bytes to be
read, while the register 0xFF buffers the message stream. The 0xFF address delivers a 0xFF byte
value if there is no data awaiting for transmission, or all the bytes have been read.
UBX-22020019 - R01
2 Receiver functionality
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