LISA-U series - System Integration Manual
UBX-13001118 - R17
Advance information
System description
Page 102 of 190
I
2
S transmit data is composed of 16 bit words, dual mono (the words are written on both channels). Data
are in 2’s complement notation. MSB is transmitted first. The bits are written on I
2
S clock rising or falling
edge (configurable)
I
2
S receive data is read as 16 bit words, mono (words are read only on the timeslot with WA high). Data is
read in 2’s complement notation. MSB is read first. The bits are read on the I
2
S clock edge opposite to I
2
S
transmit data writing edge (configurable)
I
2
S clock frequency is 16 bits x 2 channels x <sample_rate>
The modes are configurable through a specific AT command (see the
u-blox AT Commands Manual
[3], +UI2S
AT command) and the following parameters can be set:
MSB can be 1 bit delayed or non-delayed on I
2
S word alignment edge
I
2
S transmit data can change on rising or falling edge of I
2
S clock signal (rising edge in this example)
I
2
S receive data are read on the opposite front of I
2
S clock signal
1.11.2.3
I
2
S interface application circuits
LISA-U I
2
S digital audio interfaces can be connected to an external digital audio device for voice applications. The
external digital audio device must be properly configured according to the cellular module configuration, with
opposite role (i.e. master vs. slave), same mode (i.e. PCM mode or Normal I
2
S mode), same sample rate and same
voltage level.
Figure 55 shows an application circuit with a generic digital audio device.
43
I2S_CLK
41
I2S_WA
I
2
S Clock
I
2
S Word Alignment
LISA-U120
LISA-U130
LISA-U2 series
(except LISA-U200-00S)
42
I2S_TXD
44
I2S_RXD
I
2
S Data Input
I
2
S Data Output
GND
GND
1.8 V Digital
Audio Device
Figure 55: I
2
S interface application circuit with a generic digital audio device
Figure 56 and Table 47 describe an application circuit for I
2
S digital audio interfaces of LISA-U2 series modules
(except for LISA-U200-00S), providing voice capability using an external audio voice codec. DAC and ADC
integrated in the external audio codec respectively converts an incoming digital data stream to analog audio
output through a mono amplifier and converts the microphone input signal to the digital bit stream over the
digital audio interface.
An I
2
S digital audio interface of the LISA-U2 series modules (except LISA-U200-00S) that acts as an I
2
S master is
connected to the digital audio interface of the external audio codec (that acts as an I
2
S slave). The first I
2
S
interface can be used as well as the second I
2
S interface of the cellular module.
The
CODEC_CLK
digital output clock of the cellular module is connected to the clock input of the external audio
codec to provide clock reference.
Signal integrity of the high speed lines may be degraded if the PCB layout is not optimal, especially when the
CODEC_CLK
clock line or also the I
2
S digital audio interface lines are very long: keep routing short and minimize
parasitic capacitance to preserve signal integrity.
