LEA-6 / NEO-6 / MAX-6 - Hardware Integration Manual
UBX-14054794
Production Information
Appendix
Page 77 of 85
of the device. The default DDC address for u-blox GPS receivers is set to 0x42. Setting the mode field in the
CFG-PRT message for DDC accordingly can change this address.
The first byte sent is comprised of the address field and R/W bit. Hence the byte seen on the bus 0x42 is
shifted by 1 to the left plus R/W bit thus being 0x84 or 0x85 if analyzed by scope or protocol analyzer.
In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. At that time, any device addressed is considered a slave. The DDC-bus is a multi-master bus,
i.e. multiple devices are capable of controlling the bus. Such architecture is not permanent and depends on the
direction of data transfer at any given point in time. A master device not only allocates the time slots when
slaves can respond but also enables and synchronizes designated slaves to physically access the bus by driving
the clock. Although multiple nodes can assume the role of a master, only one at any time is permitted to do so.
Thus, when one node acts as master, all other nodes act as slaves. Table 33 shows the possible roles and modes
for devices connected to a DDC bus.
Transmit
Receive
Master:
sends the clock and addresses slaves
Sends data to slave
Receives data from slave
Slave:
receives the clock and address
Sends data to master
Receives data from master
Table 33: Possible roles and modes of devices connected to DDC bus
u-blox 6 GPS receivers normally run in the slave mode. There is an exception when an external EEPROM is
attached. In that case, the receiver attempts to establish presence of such a non-volatile memory component by
writing and reading from a specific location. If EEPROM is present (assumed to be located at a fixed address
0xA0), the receiver assumes the role of a master on the bus and never changes role to slave until the following
start-up (subject to EEPROM presence). This process takes place only once at the start-up, i.e. the receiver’s role
cannot be changed during the normal operation afterward. This model is an exception and should not be
implemented if there are other participants on the bus contending for the bus control (
µ
C / CPU, etc.).
As a slave on the bus, the u-blox 6 GPS receiver cannot initiate the data transfers. The master node has the
exclusive right and responsibility to generate the data clock, therefore the slave nodes need not be configured to
use the same baud rate. For the purpose of simplification, if not specified differently, SLAVE denotes the u-blox 6
GPS receiver while MASTER denotes the external device (CPU,
μ
C) controlling the DDC bus by driving the SCL
line.
u-blox GPS receivers support Standard-Mode I
2
C-bus specification with 7-bit addressing and a data
transfer rate up to 100 kBit/s and a SCL clock frequency up to 100 kHz.
C.1.2
DDC troubleshooting
Consider the following questions when implementing I
2
C in designs:
Is there a stable supply voltage Vdd? Often, external I
2
C devices (like I
2
C masters or monitors) must be
provided with Vdd.
Are appropriate termination resistances attached between SDA, SCL and Vdd? The voltage level on SDA and
SCL must be Vdd as long as the bus is idle and drop near GND if shorted to GND. [Note: Very few I
2
C
masters exist which drive SCL high and low, i.e. the SCL line is not open-drain. In this case, a termination
resistor is not needed and SCL cannot be pulled low. These masters will not work together with other
masters (as they have no multi-master support) and may not be used with devices which stretch SCL during
transfers.]
Are SDA and SCL mixed up? This may accidentally happen e.g. when connecting I
2
C buses with cables or
connectors.
Do all I
2
C devices support the I
2
C supply voltage used on the bus?
Do all I
2
C devices support the maximum SCL clock rate used on the bus?
If more than one I
2
C master is connected to the bus: do all masters provide multi-master support?
