AMY-6M - Hardware Integration Manual
UBX-17021971 – R07
Design-in
Page 10 of 57
2.1.1.6
Built-in supply voltage monitors
Built-in supply voltage monitors ensure that the system always operates within safe limits. The following
conditions need to be met in order for the system to run properly:
1.
The core voltages VDD_C and VDD_B need to be within specification. These voltages are supervised by
internal supply monitors.
2.
The I/O voltage VDD_IO needs to be within specification. This voltage is supervised by an internal supply
monitor. This supply monitor has a system configurable threshold done automatically by the Firmware.
3.
The RF supply voltage needs to be within specification. This voltage is supervised at pin V_RESET by an
internal supply monitor. The threshold of this supply monitor can be configured using the V_TH pin. If
V_TH is open, the threshold is set for a nominal supply voltage of 1.8 V, if this pin is connected to GND
the threshold is set for a nominal supply voltage of 2.5 V and above.
4.
If external memory is used, its supply voltage, i.e. VDD_IO, needs to be within the specification of this
part.
With respect to points 2 and 3 listed above, the voltage that defines the lowest operational boundary condition
of the system shall be supervised at the V_RESET pin. This is usually the RF IC supply voltage (VDD_3V). In
designs using EEPROM memory it may also be VDD_IO. Normally, higher system supply voltages take longer to
rise and fall faster than lower supply voltages, e.g. if in a given application, the RF section requires 1.8 V but
external memory requires 2.7 V, it is advisable to monitor VDD_IO rather than VDD_3V.
With respect to item 4 above the design must ensure that VDD_IO is present and within the operating range of
the external memory at system boot time. Else, the system may fail in detecting the external memory and the
memory will be ignored.
Initially at system start-up, the threshold of the VDD_IO supply monitor is set to its lowest value in order to
ensure the system only starts when I/Os are operational. Once external memory is detected, the threshold will be
adapted according to memory type in order to detect brown-out conditions in case VDD_IO would drop below
the operational range of external memory. The following rules do apply:
1.
In case of EEPROM at DDC interface, the VDD_IO threshold is set to 1.8V. All EEPROMs used with u-blox
6 must support operation down to 1.8V. Only EEPROM types listed in Table 14 must be used.
2.
In case of Serial FLASH memory at SPI interface, VDD_IO threshold is set according to its type. Only
FLASH memory types listed in Table 15 must be used.
Internally, VDD_B and VDD_C are supervised by power-on reset circuits. Reset signals on backup and core
domains are only released once the respective supply voltages fall within the operational conditions.
After release of the power-on reset on circuit at VDD_C the systems waits for 2048 clock cycles to stabilize
before the clock signal is fed into the core. This ensures system operation only with a clean clock signal.
An additional monitor switches the supply of the back-up region VDD_B (RTC and backup RAM) from VDD_IO to
V_BCKP, once VDD_IO falls below its operational specification. Thus, a separate supply source can be used to
maintain RTC and backup RAM information even if VDD_IO fails. If this feature is not needed, V_BCKP must be
connected to GND.
2.1.1.7
USB interface power supply
VDD_USB supplies the I/Os of the USB interface. If the USB interface is not used, the VDD_USB pin must be
connected to GND.
If the USB interface is being used the system can be either self-powered, i.e. powered independently from the
USB bus, or it can be bus-powered, i.e. powered through the USB connection. In bus-powered mode, the system
supply voltages need to be generated from the USB supply voltage VBUS. See section 2.3.2.
If the application uses USB, the correct USB power mode needs to be configured (bus-powered or self
powered). See the
u-blox 6 Receiver Description including Protocol Specification
