LARA-R2 series - System Integration Manual
UBX-16010573 - R02
Objective Specification
System description
Page 10 of 148
Baseband and power management section
The Baseband and Power Management section is composed of the following main elements:
A mixed signal ASIC, which integrates
Microprocessor for control functions
DSP core for cellular Layer 1 and digital processing of Rx and Tx signal paths
Memory interface controller
Dedicated peripheral blocks for control of the USB, SIM and generic digital interfaces
Interfaces to RF transceiver ASIC
Memory system, which includes NAND flash and LPDDR2 RAM
Voltage regulators to derive all the subsystem supply voltages from the module supply input
VCC
Voltage sources for external use:
V_BCKP
and
V_INT
Hardware power on
Hardware reset
Low power idle-mode support
32.768 kHz crystal oscillator to provide the clock reference in the low power idle-mode, which can be set by
enable power saving configuration using the AT+UPSV command.