Trinity KT400 S2495
Chapter 3: BIOS Setup
3-13
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CPU & PCI Bus Control:
Phoenix – AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
PCI1 Master 0 WS Write
PCI2 Master 0 WS Write
PCI1 Post Write
PCI2 Post Write
VLink 8X Support
PCI Delay Transaction
[Enabled]
[Enabled]
[Enabled]]
[Enabled]
[[Enabled]
[Enabled]
Item Help
_________________________
Menu Level ? ?
↑↓←→
: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
PCI1 Master 0 WS Write:
When “Enabled”, Write to the PCI1 bus is commanded with zero waiting states.
Enabled / Disabled
PCI2 Master 0 WS Write:
When “Enabled”, Write to the PCI2 bus is commanded with zero waiting states.
Enabled / Disabled
PCI Delay Transaction:
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select “Enabled” to support compliance with PCI specification version 2.1
Enabled / Disabled
VLink 8X Support:
Enables 533Mbytes/sec connection between South and Northbridge.
Enabled / Disabled
System BIOS Cacheable:
This option allows you to copy your BIOS code from slow ROM to fast RAM.
Enabled / Disabled
Video RAM Cacheable:
This option allows the CPU to cache read / write of the video RAM. Leave as default.
Enabled / Disabled