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Chapter 3
BIOS Configuration
Chipset Features Setup - Optimized Default Settings
Bank 0/1, 2/3, 4/5 DRAM Timing
The system board designer must select the proper value for these fields,
according to the specifications of the installed DRAM chips. Turbo mode
reduces CAS access time by 1 clock tick.
SDRAM Cycle Length
This field sets the CAS latency timing.
DRAM Clock
Allows you to set the memory clock speed to either 66MHz or equal to the
CPU clock speed, depending on your memory speed.
CMOS Setup Utility - Copyright (C) 1984-2000 Award Software
Advanced Chipset Features
Bank 0/1 DRAM Timing
SDRAM 10ns
Item Help
Bank 2/3 DRAM Timing
SDRAM 10ns
Bank 4/5 DRAM Timing
SDRAM 10ns
Menu Level
SDRAM Cycle Length
3
DRAM Clock
Host CLK
Memory Hole
Disabled
P2C/C2P Concurrency
Enabled
Fast R-W Turn Around
Disabled
System BIOS Cacheable
Disabled
Video RAM Cacheable
Disabled
AGP Aperature Size
64M
AGP-4X Mode
Enabled
AGP Driving Control
Auto
X AGP Driving Value
DA
K7 CLK_CTL Select
Optimal
OnChip USB
Enabled
USB Keyboard Support
Disabled
OnChip Sound
Auto
CPU to PCI Write Buffer
Enabled
PCI Dynamic Bursting
Enabled
PCI Master 0 WS Write
Enabled
PCI Delay Transaction
Enabled
PCI#2 Access #1 Retry
Disabled
AGP Master 1 WS Write
Disabled
AGP Master 1 WS Read
Disabled
Memory Parity/ECC Check
Disabled
↑ ↓ → ←
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
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