TE0712 TRM
Revision: V14
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On-board Peripherals
32 MByte Quad SPI Flash Memory
On-board QSPI flash memory S25FL256S (U14) is used to store initial FPGA configuration. Besides FPGA
configuration, remaining free flash memory can be used for user application and data storage. All four SPI
data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends
on the selected bus width and clock frequency used.
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration
from flash during power-on. By default this bit is set to high at the manufacturing plant.
System Controller CPLD
System Controller CPLD (Lattice MachXO2-256HC, U3) is used to control FPGA configuration process. The
FPGA is held in reset (by driving the PROG_B signal low) until all power supplies have stabilized.
By driving signal RESIN to low you can reset the FPGA. This signal can be driven from the user’s
baseboard PCB via the B2B connector JM2 pin 18.
Input EN1 is also gated to FPGA reset, should be open or pulled up for normal operation. By driving EN1
low, on-board DC-DC converters will be not turned off.
User can create their own System Controller design using
software. Once created it can be
programmed into CPLD via JTAG interface.
DDR3 SDRAM
The TE0712-02 SoM has two 4 Gbit volatile DDR3 SDRAM ICs (U15 and U19) for storing user application
code and data.
Part number: IM4G16D3FABG-125I
Supply voltage: 1.5V
Organization: 32M words x 16 bits x 8 banks
Memory speed: limited by Xilinx Artix-7 speed grade and MIG
Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx
Vivado Design Suite IP catalog.
