Transcend TS-AVD1, Руководство пользователя

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BIOS SETUP
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- PCI/ISA PnP devices, whether designed for PCI or ISA bus architecture, compliant with the
Plug and Play standard.
•
DMA-n Assigned to
When resources are controlled manually, assign each system DMA channel as one of the
following types, depending on the type of device using the DMA.
- Legacy ISA Devices, requiring a specific DMA channel, compliant with the original PCAT
bus specification.
- PCI/ISA PnP devices, whether designed for PCI or ISA bus architecture, compliant with
the Plug and Play standard.
•
CPU to PCI Write Buffer
When “Enabled”, up to four Dword of data can be written to the PCI bus without waiting for the
PCI bus finish. When “Disabled”, a write buffer is not used and the CPU must wait after each
write cycle until the PCI bus signals that it is ready to receive more data.
•
PCI Dynamic Bursting
When “Enabled”, every write transaction goes to the write buffer. Burstable transactions then
burst on the PCI bus and nonburstable transactions will write to PCI bus immediately.
•
PCI Master 0 WS Write
When “Enabled”, writes to the PCI bus are executed with zero wait states.
•
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select “Enabled” to support compliance with PCI specification version 2.1.
•
PCI #2 Access #1 Retry
Select “Enabled” to support PCI #2 (AGP bus) access to PCI #1 (PCI bus) retry function
when a error occurred. The default value is “Disabled”.
•
AGP Master 1 WS Write
Selecting “Enabled” will implement a single delay when writing to the AGP Bus. By default,
two wait states are used by the system, allowing for greater stability.
•
AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By default, two-wait states
are used by the system, allowing for greater stability.