background image

T

T

T

S

S

S

2

2

2

G

G

G

S

S

S

D

D

D

1

1

1

5

5

5

0

0

0

 

 

 

                           

2GB 150x Secure Digital Card

 
 

Transcend Information Inc.

 

 

11

AC/DC Character 

 

• 

General 

Parameter 

Symbol

Min. 

Max. 

Unit 

Remark 

Peak voltage on all lines 

 

-0.3 VDD+0.3

 

All Inputs 
Input Leakage Current 

 

-10 10 µA 

 

All Outputs 
Output Leakage Current 

 

-10 10 µA 

 

 

• 

Power Supply Voltage 

Parameter 

Symbol

Min. 

Max. 

Unit 

Remark 

Supply voltage 

V

DD

2.0 3.6  V 

CMD0, 

15,55,ACMD41 

commands 

Supply voltage specified in OCR register 

 

2.7 

3.6 

Except CMD0, 15,55, 
ACMD41 commands 

Supply voltage differentials (V

SS1

, V

SS2

)  -0.3 

0.3 V 

 

Power up time 

 

 

250 

ms 

From 0v to V

DD

 

Min. 

 

 

• 

Bus Signal Line Load 

The total capacitance C

L

 

the CLK line of the SD Memory Card bus is the sum of the bus master capacitance C

HOST

, the bus 

capacitance C

BUS

 

itself and the capacitance C

CARD

 

of each card connected to this line: 

C

L

 

= C

HOST

 

+ C

BUS

 

Ν

*C

CARD

 

 
 

 

Parameter 

Symbol

Min. 

Max. 

Unit 

Remark 

Bus signal line capacitance 

C

L

 100 

pF 

f

PP

 

≤ 

20 MHz, 7 cards 

Single card capacitance 

C

CARD

 10 

pF 

 

Maximum signal line inductance 

 

 

16 

nH 

f

PP

 

≤ 

20 MHz 

Pull-up resistance inside card (pin1) 

R

DAT3

10 90 k

Ω

 

May be used for card 
detection 

 

Note that the total capacitance of CMD and DAT lines will be consist of C

HOST

, C

BUS

 and one C

CARD

 only since they are 

connected separately to the SD Memory Card host. 

 

Parameter 

Symbol

Min. 

Max. 

Unit 

Remark 

Pull-up resistance 

R

CMD

, R

DAT

10 100 k

Ω

 

To prevent bus floating 

Bus signal line capacitance 

C

L

 250 

pF 

f

PP

 

≤ 

5 MHz, 21 cards 

Содержание Secure Digital Card TS2GSD150

Страница 1: ...25 85 C Insertion removal durability 10 000 cycles Fully compatible with SD card spec v1 1 Mechanical Write Protection Switch Support clock frequencies 0 50MHz Support different Bus width x1 x4 Suppor...

Страница 2: ...T T TS S S2 2 2G G GS S SD D D1 1 15 5 50 0 0 2GB 150x Secure Digital Card Transcend Information Inc 2 Architecture...

Страница 3: ...ta data can be transferred from the card to the host or vice versa Data is transferred via the data lines Figure 4 no response and no data operations Card addressing is implemented using a session add...

Страница 4: ...data lines used for transferring the data Figure 6 Multiple Block write operation Command tokens have the following coding scheme Figure 7 Command token format Each command token is preceded by a sta...

Страница 5: ...is transmitted first the LSB bit is the last When the wide bus option is used the data is transferred 4 bits at a time refer to Figure 10 Start and end bits as well as the CRC bits are transmitted for...

Страница 6: ...t will respond with an error response which replaces the expected data block rather than by a time out as in the SD mode In addition to the command response every data block sent to the card during wr...

Страница 7: ...e token and will wait for a data block to be sent from the host CRC suffix block length and start address restrictions are identical to the read operation see Figure 13 Figure 13 Write operation After...

Страница 8: ...0000 b 7 1 65V 1 95V 0 b 14 8 2 0V 2 6V 000 0000 b 23 15 2 7V 3 6V 1 1111 1111 b 30 24 Reserved 000 0000 b 31 Card power status bit 1 OCR bit 31 is set to LOW if the card has not finished the power u...

Страница 9: ...erved 119 112 8 Data read access time 1 TAAC 7F h 80 ms 111 104 8 Data read access time 2 NSAC FF h 25 5k clocks 103 96 8 Max bus clock freq TRAN_SPEED 32 h 25 MHz 95 84 12 Card command classes CCC 1F...

Страница 10: ...4 This field is not a constant value The value will be changed by different flash memory 6 Extended CSD Register EXT_CSD The Extended CSD register defines the card properties and selected modes It is...

Страница 11: ...total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST the bus capacitance CBUS itself and the capacitance CCARD of each card connected to this lin...

Страница 12: ...ly voltage To meet the requirements of the JEDEC specification JESD8 1A the card input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range Param...

Страница 13: ...min VIH and max VIL Clock frequency Data Transfer Mode fPP 0 25 MHz CL 100 pF 7 cards Clock frequency Identification Mode The low freq is required for MultiMediaCard compatibility fOD 0 400 KHz CL 25...

Страница 14: ...cards Clock fall time 50 ns CL 250 pF 21 cards Inputs CMD DAT referenced to CLK Input set up time tISU 5 ns CL 25 pF 1 cards Input hold time tIH 5 ns CL 25 pF 1 cards Outputs CMD DAT referenced to CLK...

Страница 15: ...Min Max Unit Remark Clock CLK All values are referred to min VIH and max VIL Clock frequency Data Transfer Mode fPP 0 50 MHz Clock low time tWL 7 ns Clock high time tWH 7 ns Clock rise time tTLH 3 ns...

Страница 16: ...GS S SD D D1 1 15 5 50 0 0 2GB 150x Secure Digital Card Transcend Information Inc 16 Output Delay time during Data Transfer Mode tODLY 14 ns Output Hold time tOH 2 5 ns Total System capacitance for e...

Страница 17: ...UV light exposure UV 254nm 15Ws cm according to ISO 7816 1 Visual inspection Shape and form No warp page no mold skin complete form no cavities surface smoothness 0 1 mm cm within contour no cracks no...

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