TQ-Systems MBLX2160A, Руководство пользователя

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User's Manual l MBLX2160A UM 0101 l © 2022, TQ-Systems GmbH Page 9
3.1.2 TQMLX2160A pinout (continued)
Table 4: Connector X2, MBLX2160A (continued)
Dir. Level Group Signal Pin Signal Group Level Dir.
I – USB2 USB2_RX_N A56 B56 DGND Ground 0 V –
– 0 V Ground DGND A57 B57 USB2_PWRFAULT USB2 1.8 V I/O
I/O – USB2 USB2_DP A58 B58 USB2_DRVBUS USB2 1.8 V I/O
I/O – USB2 USB2_DN A59 B59 USB2_VBUS USB2 5 V I
– 0 V Ground DGND A60 B60 DGND Ground 0 V –
– 0 V Ground DGND A61 B61 DGND Ground 0 V –
I – SERDES3 SD3_PLLF_REFCLK_P A62 B62 SD3_PLLS_REFCLK_P SERDES3 – I
I – SERDES3 SD3_PLLF_REFCLK_N A63 B63 SD3_PLLS_REFCLK_N SERDES3 – I
– 0 V Ground DGND A64 B64 DGND Ground 0 V –
O – SERDES3 SD3_TX0_P A65 B65 SD3_RX0_P SERDES3 – I
O – SERDES3 SD3_TX0_N A66 B66 SD3_RX0_N SERDES3 – I
– 0 V Ground DGND A67 B67 DGND Ground 0 V –
O – SERDES3 SD3_TX1_P A68 B68 SD3_RX1_P SERDES3 – I
O – SERDES3 SD3_TX1_N A69 B69 SD3_RX1_N SERDES3 – I
– 0 V Ground DGND A70 B70 DGND Ground 0 V –
– 0 V Ground DGND A71 B71 DGND Ground 0 V –
O – SERDES3 SD3_TX2_P A72 B72 SD3_RX2_P SERDES3 – I
O – SERDES3 SD3_TX2_N A73 B73 SD3_RX2_N SERDES3 – I
– 0 V Ground DGND A74 B74 DGND Ground 0 V –
O – SERDES3 SD3_TX3_P A75 B75 SD3_RX3_P SERDES3 – I
O – SERDES3 SD3_TX3_N A76 B76 SD3_RX3_N SERDES3 – I
– 0 V Ground DGND A77 B77 DGND Ground 0 V –
O – SERDES3 SD3_TX4_P A78 B78 SD3_RX4_P SERDES3 – I
O – SERDES3 SD3_TX4_N A79 B79 SD3_RX4_N SERDES3 – I
– 0 V Ground DGND A80 B80 DGND Ground 0 V –
– 0 V Ground DGND A81 B81 DGND Ground 0 V –
O – SERDES3 SD3_TX5_P A82 B82 SD3_RX5_P SERDES3 – I
O – SERDES3 SD3_TX5_N A83 B83 SD3_RX5_N SERDES3 – I
– 0 V Ground DGND A84 B84 DGND Ground 0 V –
O – SERDES3 SD3_TX6_P A85 B85 SD3_RX6_P SERDES3 – I
O – SERDES3 SD3_TX6_N A86 B86 SD3_RX6_N SERDES3 – I
– 0 V Ground DGND A87 B87 DGND Ground 0 V –
O – SERDES3 SD3_TX7_P A88 B88 SD3_RX7_P SERDES3 – I
O – SERDES3 SD3_TX7_N A89 B89 SD3_RX7_N SERDES3 – I
– 0 V Ground DGND A90 B90 DGND Ground 0 V –
– 0 V Ground DGND A91 B91 DGND Ground 0 V –
I/O 1.8 V SDHC2 SDHC2_MOD_CLK A92 B92 SDHC2_DATA0 SDHC2 1.8 V I/O
– 0 V Ground DGND A93 B93 SDHC2_DATA1 SDHC2 1.8 V I/O
I/O 1.8 V SDHC2 SDHC2_MOD_DS A94 B94 SDHC2_DATA2 SDHC2 1.8 V I/O
– 0 V Ground DGND A95 B95 SDHC2_DATA3 SDHC2 1.8 V I/O
I/O 1.8 V SDHC2 SDHC2_MOD_CMD A96 B96 SDHC2_DATA4 SDHC2 1.8 V I/O
– 0 V Ground DGND A97 B97 SDHC2_DATA5 SDHC2 1.8 V I/O
– 0 V Ground DGND A98 B98 SDHC2_DATA6 SDHC2 1.8 V I/O
– 0 V Ground DGND A99 B99 SDHC2_DATA7 SDHC2 1.8 V I/O
– 0 V Ground DGND A100 B100 DGND Ground 0 V –
I 3.3 V CONFIG LX_CONFIG_RFU1 A101 B101 DGND Ground 0 V –
I 3.3 V CONFIG LX_CONFIG_RFU2 A102 B102 TB_SCAN_EN# TEST 1.8 V I
I 3.3 V CONFIG LX_CONFIG_RFU3 A103 B103 DGND Ground 0 V –
I 3.3 V CONFIG LX_CONFIG_RFU4 A104 B104 JTAG_LX_HRESET JTAG_CPU 1.8 V I
I 3.3 V CONFIG LX_CONFIG_RFU5 A105 B105 JTAG_LX_TDI JTAG_CPU 1.8 V I
– 0 V Ground DGND A106 B106 JTAG_LX_TDO JTAG_CPU 1.8 V O
I/O 1.8 V I2C I2C6_CPU_SCL A107 B107 JTAG_LX_TMS JTAG_CPU 1.8 V I
I/O 1.8 V I2C I2C5_CPU_SDA A108 B108 JTAG_LX_TRST# JTAG_CPU 1.8 V I
O 1.8 V JTAG_CPU JTAG_LX_VREF A109 B109 JTAG_LX_TCK JTAG_CPU 1.8 V I
– 0 V Ground DGND A110 B110 DGND Ground 0 V –