
TC32306FTG
2015-10-01
42
6.7.9 EEPROM Mode Signal Timings
Fig 6-25 Example of EEPROM Control Timing
Fig 6-26 Example of EEPROM Output Timing
Fig 6-27 Example of EEPROM Input Timing
The timing chart for explaining the operation of features and may have been simplified.
CS
t
CSD
RESET
t
CSWH
t
CSWH
(1)
(2)
(3)
* This IC repeats three times to read configuration
data from the EEPROM for the majority logic.
CS
CLK
MOSI
MISO
t
CKD
t
CSD
t
CKWH
t
CKWL
t
MOS
t
MOD
MSB OUT
t
CKF
t
CKR
RESET
LSB OUT
t
MOD
t
MOS
(1)
CS
CLK
MOSI
MISO
t
CKWH
t
CKWL
t
CSH
t
CKF
t
CKR
MSB IN
LSB OUT
LSB IN
t
CSH
t
MID
t
MIH
(1)
t
MIS